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author | Andrew Trick <atrick@apple.com> | 2011-03-05 08:00:22 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2011-03-05 08:00:22 +0000 |
commit | e0ef509aeb47b396cf1bdc170ca4f468f799719f (patch) | |
tree | be309e6cc6e8a6f933206cba78de2930eba7a668 /include | |
parent | a4a1c3f0d92f8737b5ff72bfd4b44bf19c859cee (diff) | |
download | llvm-e0ef509aeb47b396cf1bdc170ca4f468f799719f.tar.gz llvm-e0ef509aeb47b396cf1bdc170ca4f468f799719f.tar.bz2 llvm-e0ef509aeb47b396cf1bdc170ca4f468f799719f.tar.xz |
Increased the register pressure limit on x86_64 from 8 to 12
regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.
Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.
Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127067 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index fc7b51ec6c..13bcee652f 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -641,6 +641,10 @@ public: virtual int getInstrLatency(const InstrItineraryData *ItinData, SDNode *Node) const; + /// isHighLatencyDef - Return true if this opcode has high latency to its + /// result. + bool isHighLatencyDef(int opc) const { return false; } + /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' /// and an use in the current loop, return true if the target considered /// it 'high'. This is used by optimization passes such as machine LICM to |