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author | Rafael Espindola <rafael.espindola@gmail.com> | 2010-07-12 02:55:34 +0000 |
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committer | Rafael Espindola <rafael.espindola@gmail.com> | 2010-07-12 02:55:34 +0000 |
commit | 7e1b566322ecb5ff752c9a5f2feb503b6fb75262 (patch) | |
tree | d22f10e0443db0539bbffe6e8a0a6fae29511348 /lib/CodeGen/AggressiveAntiDepBreaker.cpp | |
parent | 688d58033a077dd05be830cd23f8d416ce1be59d (diff) | |
download | llvm-7e1b566322ecb5ff752c9a5f2feb503b6fb75262.tar.gz llvm-7e1b566322ecb5ff752c9a5f2feb503b6fb75262.tar.bz2 llvm-7e1b566322ecb5ff752c9a5f2feb503b6fb75262.tar.xz |
Convert the last use of getPhysicalRegisterRegClass and remove it.
AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An
instruction might be using a register that can only be replaced with one from
a subclass of getPhysicalRegisterRegClass.
With this patch we use getMinimalPhysRegClass. This is correct, but
conservative. We should check the uses of the register and select the
largest register class that can be used in all of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108122 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/AggressiveAntiDepBreaker.cpp')
-rw-r--r-- | lib/CodeGen/AggressiveAntiDepBreaker.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/lib/CodeGen/AggressiveAntiDepBreaker.cpp index 7d923b1258..a7189acc3f 100644 --- a/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -626,8 +626,12 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // order. If that register is available, and the corresponding // registers are available for the other group subregisters, then we // can use those registers to rename. + + // FIXME: Using getMinimalPhysRegClass is very conservative. We should + // check every use of the register and find the largest register class + // that can be used in all of them. const TargetRegisterClass *SuperRC = - TRI->getPhysicalRegisterRegClass(SuperReg, MVT::Other); + TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); const TargetRegisterClass::iterator RB = SuperRC->allocation_order_begin(MF); const TargetRegisterClass::iterator RE = SuperRC->allocation_order_end(MF); |