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authorPekka Jaaskelainen <pekka.jaaskelainen@tut.fi>2013-10-15 14:40:46 +0000
committerPekka Jaaskelainen <pekka.jaaskelainen@tut.fi>2013-10-15 14:40:46 +0000
commitd54946ac14cca14a0b4402fd7edf5271f5e74e6a (patch)
treebe6ea0ac7bb5b14ae6456b678c2e4016f10aae26 /lib/CodeGen/MachineInstr.cpp
parent862385112e4f81ca2e1ffb3e995c223ffd5328b7 (diff)
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Guard the debug temp variable with NDEBUG to avoid warning/error with NDEBUG defined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192709 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineInstr.cpp')
-rw-r--r--lib/CodeGen/MachineInstr.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 488516385d..295b450a0f 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -647,6 +647,7 @@ void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
}
}
+#ifndef NDEBUG
bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
// OpNo now points as the desired insertion point. Unless this is a variadic
// instruction, only implicit regs are allowed beyond MCID->getNumOperands().
@@ -654,6 +655,7 @@ void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
OpNo < MCID->getNumOperands() || isMetaDataOp) &&
"Trying to add an operand to a machine instr that is already done!");
+#endif
MachineRegisterInfo *MRI = getRegInfo();