Add an analyzeVirtReg() function.

This function does more or less the same as
MI::readsWritesVirtualRegister(), but it supports bundles as well.

It also determines if any constraint requires reading and writing
operands to use the same register.  Most clients want to know.

Use the more modern MO.readsReg() instead of trying to sort out undefs
and partial redefines.  Stop supporting the extra full <imp-def> operand
as an alternative to <def,undef> sub-register defines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151690 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 33 insertions, 0 deletions

diff --git a/lib/CodeGen/MachineInstrBundle.cpp b/lib/CodeGen/MachineInstrBundle.cpp
index d8b2b3a6ce..81d2abeb1d 100644
--- a/lib/CodeGen/MachineInstrBundle.cpp
+++ b/lib/CodeGen/MachineInstrBundle.cpp
@@ -241,3 +241,36 @@ bool llvm::finalizeBundles(MachineFunction &MF) {
 
   return Changed;
 }
+
+//===----------------------------------------------------------------------===//
+// MachineOperand iterator
+//===----------------------------------------------------------------------===//
+
+MachineOperandIteratorBase::RegInfo
+MachineOperandIteratorBase::analyzeVirtReg(unsigned Reg,
+                    SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) {
+  RegInfo RI = { false, false, false };
+  for(; isValid(); ++*this) {
+    MachineOperand &MO = deref();
+    if (!MO.isReg() || MO.getReg() != Reg)
+      continue;
+
+    // Remember each (MI, OpNo) that refers to Reg.
+    if (Ops)
+      Ops->push_back(std::make_pair(MO.getParent(), getOperandNo()));
+
+    // Both defs and uses can read virtual registers.
+    if (MO.readsReg()) {
+      RI.Reads = true;
+      if (MO.isDef())
+        RI.Tied = true;
+    }
+
+    // Only defs can write.
+    if (MO.isDef())
+      RI.Writes = true;
+    else if (!RI.Tied && MO.getParent()->isRegTiedToDefOperand(getOperandNo()))
+      RI.Tied = true;
+  }
+  return RI;
+}