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authorRafael Espindola <rafael.espindola@gmail.com>2013-10-14 16:39:04 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2013-10-14 16:39:04 +0000
commit67b28826cdc7be697acdd3e536a05665fd2a9752 (patch)
tree2077ea88a1e330aa67fb2bf03b9a1136f5f03219 /lib/CodeGen/Passes.cpp
parent2a6cbba2db261d2ee29a1373e195f95fd232e61b (diff)
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Remove the now unused strong phi elimination pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192604 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/Passes.cpp')
-rw-r--r--lib/CodeGen/Passes.cpp17
1 files changed, 3 insertions, 14 deletions
diff --git a/lib/CodeGen/Passes.cpp b/lib/CodeGen/Passes.cpp
index 84eb8b876f..f4ffd03ec3 100644
--- a/lib/CodeGen/Passes.cpp
+++ b/lib/CodeGen/Passes.cpp
@@ -58,8 +58,6 @@ OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
static cl::opt<cl::boolOrDefault>
EnableMachineSched("enable-misched", cl::Hidden,
cl::desc("Enable the machine instruction scheduling pass."));
-static cl::opt<bool> EnableStrongPHIElim("strong-phi-elim", cl::Hidden,
- cl::desc("Use strong PHI elimination."));
static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
cl::Hidden,
cl::desc("Disable Machine LICM"));
@@ -675,24 +673,15 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
// preferably fix the scavenger to not depend on them).
addPass(&LiveVariablesID);
- // Add passes that move from transformed SSA into conventional SSA. This is a
- // "copy coalescing" problem.
- //
- if (!EnableStrongPHIElim) {
- // Edge splitting is smarter with machine loop info.
- addPass(&MachineLoopInfoID);
- addPass(&PHIEliminationID);
- }
+ // Edge splitting is smarter with machine loop info.
+ addPass(&MachineLoopInfoID);
+ addPass(&PHIEliminationID);
// Eventually, we want to run LiveIntervals before PHI elimination.
if (EarlyLiveIntervals)
addPass(&LiveIntervalsID);
addPass(&TwoAddressInstructionPassID);
-
- if (EnableStrongPHIElim)
- addPass(&StrongPHIEliminationID);
-
addPass(&RegisterCoalescerID);
// PreRA instruction scheduling.