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| author | Craig Topper <craig.topper@gmail.com> | 2012-02-22 05:59:10 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-02-22 05:59:10 +0000 |
| commit | 44d23825d61d530b8d562329ec8fc2d4f843bb8d (patch) | |
| tree | db60d92a0a5df6a6a1c3d1a247a1fae22bc14796 /lib/CodeGen/PostRASchedulerList.cpp | |
| parent | b84d540bc9d70de00b791d0e0deab410d6ba3ad5 (diff) | |
| download | llvm-44d23825d61d530b8d562329ec8fc2d4f843bb8d.tar.gz llvm-44d23825d61d530b8d562329ec8fc2d4f843bb8d.tar.bz2 llvm-44d23825d61d530b8d562329ec8fc2d4f843bb8d.tar.xz | |
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/PostRASchedulerList.cpp')
| -rw-r--r-- | lib/CodeGen/PostRASchedulerList.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index a52aa75221..1f7833c47d 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -134,7 +134,7 @@ namespace { MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, AliasAnalysis *AA, const RegisterClassInfo&, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, - SmallVectorImpl<TargetRegisterClass*> &CriticalPathRCs); + SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs); ~SchedulePostRATDList(); @@ -184,7 +184,7 @@ SchedulePostRATDList::SchedulePostRATDList( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, - SmallVectorImpl<TargetRegisterClass*> &CriticalPathRCs) + SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs) : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), Topo(SUnits), AA(AA), KillIndices(TRI->getNumRegs()) { @@ -216,7 +216,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { // Check for explicit enable/disable of post-ra scheduling. TargetSubtargetInfo::AntiDepBreakMode AntiDepMode = TargetSubtargetInfo::ANTIDEP_NONE; - SmallVector<TargetRegisterClass*, 4> CriticalPathRCs; + SmallVector<const TargetRegisterClass*, 4> CriticalPathRCs; if (EnablePostRAScheduler.getPosition() > 0) { if (!EnablePostRAScheduler) return false; |