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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-16 17:42:25 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-16 17:42:25 +0000 |
commit | 79c890f64f3b67f9b11341aa452c4302b75184aa (patch) | |
tree | ba0a00dad7a0ae4352ed25d92e1b27aa46c49baa /lib/CodeGen/RegisterClassInfo.cpp | |
parent | 1e85ef645d388a8900320b81c0e6e8afb8804b06 (diff) | |
download | llvm-79c890f64f3b67f9b11341aa452c4302b75184aa.tar.gz llvm-79c890f64f3b67f9b11341aa452c4302b75184aa.tar.bz2 llvm-79c890f64f3b67f9b11341aa452c4302b75184aa.tar.xz |
Add TargetRegisterInfo::getRawAllocationOrder().
This virtual function will replace allocation_order_begin/end as the one
to override when implementing custom allocation orders. It is simpler to
have one function return an ArrayRef than having two virtual functions
computing different ends of the same array.
Use getRawAllocationOrder() in place of allocation_order_begin() where
it makes sense, but leave some clients that look like they really want
the filtered allocation orders from RegisterClassInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133170 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegisterClassInfo.cpp')
-rw-r--r-- | lib/CodeGen/RegisterClassInfo.cpp | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/lib/CodeGen/RegisterClassInfo.cpp b/lib/CodeGen/RegisterClassInfo.cpp index 5621dfe732..5a77e47bc5 100644 --- a/lib/CodeGen/RegisterClassInfo.cpp +++ b/lib/CodeGen/RegisterClassInfo.cpp @@ -81,11 +81,9 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { // FIXME: Once targets reserve registers instead of removing them from the // allocation order, we can simply use begin/end here. - TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF); - TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF); - - for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { - unsigned PhysReg = *I; + ArrayRef<unsigned> RawOrder = RC->getRawAllocationOrder(*MF); + for (unsigned i = 0; i != RawOrder.size(); ++i) { + unsigned PhysReg = RawOrder[i]; // Remove reserved registers from the allocation order. if (Reserved.test(PhysReg)) continue; |