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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-11-29 00:26:11 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-11-29 00:26:11 +0000 |
commit | 89bea17af235ea3a69485e73e54e71053c1bd936 (patch) | |
tree | 7750033b9209a378c02d8b1d94a688be5893c805 /lib/CodeGen/RegisterCoalescer.cpp | |
parent | 7b09b97bdf575e7d392435f931f767dfa6ab3c9e (diff) | |
download | llvm-89bea17af235ea3a69485e73e54e71053c1bd936.tar.gz llvm-89bea17af235ea3a69485e73e54e71053c1bd936.tar.bz2 llvm-89bea17af235ea3a69485e73e54e71053c1bd936.tar.xz |
Avoid rewriting instructions twice.
This could cause miscompilations in targets where sub-register
composition is not always idempotent (ARM).
<rdar://problem/12758887>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168837 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegisterCoalescer.cpp')
-rw-r--r-- | lib/CodeGen/RegisterCoalescer.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index 9b52d9b126..be8c098f34 100644 --- a/lib/CodeGen/RegisterCoalescer.cpp +++ b/lib/CodeGen/RegisterCoalescer.cpp @@ -887,8 +887,17 @@ void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg, // Update LiveDebugVariables. LDV->renameRegister(SrcReg, DstReg, SubIdx); + SmallPtrSet<MachineInstr*, 8> Visited; for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg); MachineInstr *UseMI = I.skipInstruction();) { + // Each instruction can only be rewritten once because sub-register + // composition is not always idempotent. When SrcReg != DstReg, rewriting + // the UseMI operands removes them from the SrcReg use-def chain, but when + // SrcReg is DstReg we could encounter UseMI twice if it has multiple + // operands mentioning the virtual register. + if (SrcReg == DstReg && !Visited.insert(UseMI)) + continue; + SmallVector<unsigned,8> Ops; bool Reads, Writes; tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops); |