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author | Andrew Trick <atrick@apple.com> | 2013-08-30 04:31:01 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2013-08-30 04:31:01 +0000 |
commit | 1362dcb5899bc88f0e567dd10e2e9003a79ace21 (patch) | |
tree | f448d4843eff1df0705397bc111802aed49cc2b3 /lib/CodeGen/RegisterPressure.cpp | |
parent | da6fc15f0fb26ebbe42ab96e0d066bbd5bdbb72e (diff) | |
download | llvm-1362dcb5899bc88f0e567dd10e2e9003a79ace21.tar.gz llvm-1362dcb5899bc88f0e567dd10e2e9003a79ace21.tar.bz2 llvm-1362dcb5899bc88f0e567dd10e2e9003a79ace21.tar.xz |
Replace LiveInterval::killedAt with isKilledAtInstr.
Return true for LRGs that end at EarlyClobber or Register slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189642 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegisterPressure.cpp')
-rw-r--r-- | lib/CodeGen/RegisterPressure.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/CodeGen/RegisterPressure.cpp b/lib/CodeGen/RegisterPressure.cpp index 188750dbc0..8328b500af 100644 --- a/lib/CodeGen/RegisterPressure.cpp +++ b/lib/CodeGen/RegisterPressure.cpp @@ -496,7 +496,7 @@ bool RegPressureTracker::recede(PressureDiff *PDiff) { // Adjust liveouts if LiveIntervals are available. if (RequireIntervals) { const LiveInterval *LI = getInterval(Reg); - if (LI && !LI->killedAt(SlotIdx)) + if (LI && !LI->isKilledAtInstr(SlotIdx)) discoverLiveOut(Reg); } increaseRegPressure(Reg); @@ -550,7 +550,7 @@ bool RegPressureTracker::advance() { bool lastUse = false; if (RequireIntervals) { const LiveInterval *LI = getInterval(Reg); - lastUse = LI && LI->killedAt(SlotIdx); + lastUse = LI && LI->isKilledAtInstr(SlotIdx); } else { // Allocatable physregs are always single-use before register rewriting. @@ -886,7 +886,7 @@ void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) { // to be bottom-scheduled to avoid searching uses at each query. SlotIndex CurrIdx = getCurrSlot(); const LiveInterval *LI = getInterval(Reg); - if (LI && LI->killedAt(SlotIdx) + if (LI && LI->isKilledAtInstr(SlotIdx) && !findUseBetween(Reg, CurrIdx, SlotIdx, MRI, LIS)) { decreaseRegPressure(Reg); } |