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author | Pedro Artigas <partigas@apple.com> | 2013-11-08 22:46:28 +0000 |
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committer | Pedro Artigas <partigas@apple.com> | 2013-11-08 22:46:28 +0000 |
commit | d900b1179535298510490030a5d2ecce93f79eb0 (patch) | |
tree | 318d810b7d16b194f189a817a707ef245f3ac05d /lib/CodeGen/RegisterPressure.cpp | |
parent | dc7eb3e023e34adc9d40e93626467cfe22756f4c (diff) | |
download | llvm-d900b1179535298510490030a5d2ecce93f79eb0.tar.gz llvm-d900b1179535298510490030a5d2ecce93f79eb0.tar.bz2 llvm-d900b1179535298510490030a5d2ecce93f79eb0.tar.xz |
increase the accuracy of register pressure computation in the presence of dead definitions by using live intervals, if available, to identify dead definitions and proceed accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194286 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegisterPressure.cpp')
-rw-r--r-- | lib/CodeGen/RegisterPressure.cpp | 33 |
1 files changed, 27 insertions, 6 deletions
diff --git a/lib/CodeGen/RegisterPressure.cpp b/lib/CodeGen/RegisterPressure.cpp index 78985d475c..092ecdd9bb 100644 --- a/lib/CodeGen/RegisterPressure.cpp +++ b/lib/CodeGen/RegisterPressure.cpp @@ -498,10 +498,20 @@ bool RegPressureTracker::recede(SmallVectorImpl<unsigned> *LiveUses, // TODO: consider earlyclobbers? for (unsigned i = 0, e = RegOpers.Defs.size(); i < e; ++i) { unsigned Reg = RegOpers.Defs[i]; - if (LiveRegs.erase(Reg)) - decreaseRegPressure(Reg); - else - discoverLiveOut(Reg); + bool DeadDef = false; + if (RequireIntervals) { + const LiveRange *LR = getLiveRange(Reg); + if (LR) { + LiveQueryResult LRQ = LR->Query(SlotIdx); + DeadDef = LRQ.isDeadDef(); + } + } + if (!DeadDef) { + if (LiveRegs.erase(Reg)) + decreaseRegPressure(Reg); + else + discoverLiveOut(Reg); + } } // Generate liveness for uses. @@ -702,8 +712,19 @@ void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) { // Kill liveness at live defs. for (unsigned i = 0, e = RegOpers.Defs.size(); i < e; ++i) { unsigned Reg = RegOpers.Defs[i]; - if (!containsReg(RegOpers.Uses, Reg)) - decreaseRegPressure(Reg); + bool DeadDef = false; + if (RequireIntervals) { + const LiveRange *LR = getLiveRange(Reg); + if (LR) { + SlotIndex SlotIdx = LIS->getInstructionIndex(MI); + LiveQueryResult LRQ = LR->Query(SlotIdx); + DeadDef = LRQ.isDeadDef(); + } + } + if (!DeadDef) { + if (!containsReg(RegOpers.Uses, Reg)) + decreaseRegPressure(Reg); + } } // Generate liveness for uses. for (unsigned i = 0, e = RegOpers.Uses.size(); i < e; ++i) { |