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| author | Dan Gohman <gohman@apple.com> | 2009-02-11 04:27:20 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-02-11 04:27:20 +0000 |
| commit | 47ac0f0c7c39289f5970688154e385be22b7f293 (patch) | |
| tree | b5171c709044c112ff2b4c1ebd44d1cd1f5f89f4 /lib/CodeGen/ScheduleDAGEmit.cpp | |
| parent | ca70533d3daeda66f6a0f19faf6691c20b34d086 (diff) | |
| download | llvm-47ac0f0c7c39289f5970688154e385be22b7f293.tar.gz llvm-47ac0f0c7c39289f5970688154e385be22b7f293.tar.bz2 llvm-47ac0f0c7c39289f5970688154e385be22b7f293.tar.xz | |
When scheduling a block in parts, keep track of the overall
instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.
Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/ScheduleDAGEmit.cpp')
| -rw-r--r-- | lib/CodeGen/ScheduleDAGEmit.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/CodeGen/ScheduleDAGEmit.cpp b/lib/CodeGen/ScheduleDAGEmit.cpp index 0c8435da6c..770f5bbbdb 100644 --- a/lib/CodeGen/ScheduleDAGEmit.cpp +++ b/lib/CodeGen/ScheduleDAGEmit.cpp @@ -33,7 +33,7 @@ void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) { } void ScheduleDAG::EmitNoop() { - TII->insertNoop(*BB, End); + TII->insertNoop(*BB, InsertPos); } void ScheduleDAG::EmitPhysRegCopy(SUnit *SU, @@ -54,7 +54,7 @@ void ScheduleDAG::EmitPhysRegCopy(SUnit *SU, break; } } - TII->copyRegToReg(*BB, End, Reg, VRI->second, + TII->copyRegToReg(*BB, InsertPos, Reg, VRI->second, SU->CopyDstRC, SU->CopySrcRC); } else { // Copy from physical register. @@ -63,7 +63,7 @@ void ScheduleDAG::EmitPhysRegCopy(SUnit *SU, bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second; isNew = isNew; // Silence compiler warning. assert(isNew && "Node emitted out of order - early"); - TII->copyRegToReg(*BB, End, VRBase, I->getReg(), + TII->copyRegToReg(*BB, InsertPos, VRBase, I->getReg(), SU->CopyDstRC, SU->CopySrcRC); } break; |