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author | Dan Gohman <gohman@apple.com> | 2009-09-25 20:36:54 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2009-09-25 20:36:54 +0000 |
commit | c76909abfec876c6b751d693ebd3df07df686aa0 (patch) | |
tree | bc66c4b4bc5955aa33a7c6fb19c0163ef070b08a /lib/CodeGen/ScheduleDAGEmit.cpp | |
parent | 602b0c8c17f458d2c80f2deb3c8e554d516ee316 (diff) | |
download | llvm-c76909abfec876c6b751d693ebd3df07df686aa0.tar.gz llvm-c76909abfec876c6b751d693ebd3df07df686aa0.tar.bz2 llvm-c76909abfec876c6b751d693ebd3df07df686aa0.tar.xz |
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/ScheduleDAGEmit.cpp')
-rw-r--r-- | lib/CodeGen/ScheduleDAGEmit.cpp | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/lib/CodeGen/ScheduleDAGEmit.cpp b/lib/CodeGen/ScheduleDAGEmit.cpp index 770f5bbbdb..0d15c02141 100644 --- a/lib/CodeGen/ScheduleDAGEmit.cpp +++ b/lib/CodeGen/ScheduleDAGEmit.cpp @@ -28,10 +28,6 @@ #include "llvm/Support/MathExtras.h" using namespace llvm; -void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) { - MI->addMemOperand(MF, MO); -} - void ScheduleDAG::EmitNoop() { TII->insertNoop(*BB, InsertPos); } |