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author | Evan Cheng <evan.cheng@apple.com> | 2010-10-06 06:27:31 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-06 06:27:31 +0000 |
commit | a0792de66c8364d47b0a688c7f408efb7b10f31b (patch) | |
tree | 74720b528520e7d3702afc6ed850dc6a6e1ce99e /lib/CodeGen/ScheduleDAGInstrs.cpp | |
parent | 7f5124829ffcf75f598b024ec40cc83753eb72d4 (diff) | |
download | llvm-a0792de66c8364d47b0a688c7f408efb7b10f31b.tar.gz llvm-a0792de66c8364d47b0a688c7f408efb7b10f31b.tar.bz2 llvm-a0792de66c8364d47b0a688c7f408efb7b10f31b.tar.xz |
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/ScheduleDAGInstrs.cpp')
-rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index 3d2565dd18..e01f0ab1ce 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -527,10 +527,10 @@ void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use, MachineInstr *DefMI = Def->getInstr(); int DefIdx = DefMI->findRegisterDefOperandIdx(Reg); if (DefIdx != -1) { - unsigned DefClass = DefMI->getDesc().getSchedClass(); - MachineInstr *UseMI = Use->getInstr(); - unsigned UseClass = UseMI->getDesc().getSchedClass(); + const TargetInstrDesc &DefTID = DefMI->getDesc(); + unsigned DefClass = DefTID.getSchedClass(); + MachineInstr *UseMI = Use->getInstr(); // For all uses of the register, calculate the maxmimum latency int Latency = -1; for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) { @@ -541,8 +541,7 @@ void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use, if (MOReg != Reg) continue; - int UseCycle = InstrItins->getOperandLatency(DefClass, DefIdx, - UseClass, i); + int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx, UseMI, i); Latency = std::max(Latency, UseCycle); // If we found a latency, then replace the existing dependence latency. |