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| author | Weiming Zhao <weimingz@codeaurora.org> | 2014-01-13 18:47:54 +0000 |
|---|---|---|
| committer | Weiming Zhao <weimingz@codeaurora.org> | 2014-01-13 18:47:54 +0000 |
| commit | 436f2975ace26abec6a686ef74fec728d5d52aa4 (patch) | |
| tree | e60982a9cdcfbbf5e8b370ef60de2134997f9fca /lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | |
| parent | 99c7fec2c94bd44fd16ba50340896287438e6a0e (diff) | |
| download | llvm-436f2975ace26abec6a686ef74fec728d5d52aa4.tar.gz llvm-436f2975ace26abec6a686ef74fec728d5d52aa4.tar.bz2 llvm-436f2975ace26abec6a686ef74fec728d5d52aa4.tar.xz | |
Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks
The issue is caused when Post-RA scheduler reorders a bundle instruction
(IT block). However, it only flips the CPSR liveness of the bundle instruction,
leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes
Thumb2SizeReduction.cpp::ReduceMBB().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199127 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
0 files changed, 0 insertions, 0 deletions