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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-10-12 01:24:51 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-10-12 01:24:51 +0000 |
| commit | 22e8a366adf5a4c78148928ff64e7e00c1088492 (patch) | |
| tree | cdeaee5c1150e8798f903a0ef89666170fbbdb20 /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | 41f9a430cbb47b1d6172a91d2a70adc552b65678 (diff) | |
| download | llvm-22e8a366adf5a4c78148928ff64e7e00c1088492.tar.gz llvm-22e8a366adf5a4c78148928ff64e7e00c1088492.tar.bz2 llvm-22e8a366adf5a4c78148928ff64e7e00c1088492.tar.xz | |
Use an existing function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141763 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index c6eeebe606..c2a58c6357 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2760,16 +2760,8 @@ getRegForInlineAsmConstraint(const std::string &Constraint, // If none of the value types for this register class are valid, we // can't use it. For example, 64-bit reg classes on 32-bit targets. - bool isLegal = false; - for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); - I != E; ++I) { - if (isTypeLegal(*I)) { - isLegal = true; - break; - } - } - - if (!isLegal) continue; + if (!isLegalRC(RC)) + continue; for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E; ++I) { |