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authorAndrew Trick <atrick@apple.com>2011-09-21 02:20:46 +0000
committerAndrew Trick <atrick@apple.com>2011-09-21 02:20:46 +0000
commit3be654f8082dcbdff011a6716a7c90486e28fc9e (patch)
treec8ed3778b0094ee060135ae967ad30fd478c7635 /lib/CodeGen/SelectionDAG
parente23dc9c0ef50b0a1934c04c1786f3a0478d62f41 (diff)
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Lower ARM adds/subs to add/sub after adding optional CPSR operand.
This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG')
-rw-r--r--lib/CodeGen/SelectionDAG/InstrEmitter.cpp2
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp9
2 files changed, 5 insertions, 6 deletions
diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index e2e906afa6..000a7dfcd6 100644
--- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -763,7 +763,9 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
}
// Run post-isel target hook to adjust this instruction if needed.
+#ifdef NDEBUG
if (II.hasPostISelHook())
+#endif
TLI->AdjustInstrPostInstrSelection(MI, Node);
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index b684619776..5b4ade2681 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -179,12 +179,9 @@ TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
SDNode *Node) const {
-#ifndef NDEBUG
- dbgs() << "If a target marks an instruction with "
- "'hasPostISelHook', it must implement "
- "TargetLowering::AdjustInstrPostInstrSelection!";
-#endif
- llvm_unreachable(0);
+ assert(!MI->getDesc().hasPostISelHook() &&
+ "If a target marks an instruction with 'hasPostISelHook', "
+ "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
}
//===----------------------------------------------------------------------===//