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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-06-10 16:01:25 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-06-10 16:01:25 +0000 |
| commit | c23f0e1e446426190f563fcb89ef644927f7f438 (patch) | |
| tree | 7c7035c98dce85c7eb9803ea1bd2b5f05ac53cc1 /lib/CodeGen/SelectionDAG | |
| parent | f586a260ca729c933cb15c6e68cabe95163a6dcb (diff) | |
| download | llvm-c23f0e1e446426190f563fcb89ef644927f7f438.tar.gz llvm-c23f0e1e446426190f563fcb89ef644927f7f438.tar.bz2 llvm-c23f0e1e446426190f563fcb89ef644927f7f438.tar.xz | |
SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors
This prevents a future commit from regressing:
test/CodeGen/R600/setcc-equivalent.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210540 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index b9da13af75..f1d03f752a 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2758,24 +2758,24 @@ SDValue DAGCombiner::visitAND(SDNode *N) { ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); - if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && + if (LR == RR && Op0 == Op1 && LL.getValueType().isInteger()) { // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) - if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { + if (TLI.isConstFalseVal(LR.getNode()) && Op1 == ISD::SETEQ) { SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0), LR.getValueType(), LL, RL); AddToWorkList(ORNode.getNode()); return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1); } // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) - if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { + if (TLI.isConstTrueVal(LR.getNode()) && Op1 == ISD::SETEQ) { SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0), LR.getValueType(), LL, RL); AddToWorkList(ANDNode.getNode()); return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1); } // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) - if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { + if (TLI.isConstTrueVal(LR.getNode()) && Op1 == ISD::SETGT) { SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0), LR.getValueType(), LL, RL); AddToWorkList(ORNode.getNode()); |