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author | Rafael Espindola <rafael.espindola@gmail.com> | 2014-05-28 15:30:40 +0000 |
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committer | Rafael Espindola <rafael.espindola@gmail.com> | 2014-05-28 15:30:40 +0000 |
commit | e8075c6877d1f2e1be6c2646135912406616249c (patch) | |
tree | d81d3c860f30aa2b7230f2b5a20d858f5324b5ae /lib/CodeGen/SelectionDAG | |
parent | b8af23fe1ecc74021e2cc5a3ad1ecdcbbcb65c4e (diff) | |
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InstCombine: Improvement to check if signed addition overflows.
This patch implements two things:
1. If we know one number is positive and another is negative, we return true as
signed addition of two opposite signed numbers will never overflow.
2. Implemented TODO : If one of the operands only has one non-zero bit, and if
the other operand has a known-zero bit in a more significant place than it
(not including the sign bit) the ripple may go up to and fill the zero, but
won't change the sign. e.x - (x & ~4) + 1
We make sure that we are ignoring 0 at MSB.
Patch by Suyog Sarda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209746 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG')
0 files changed, 0 insertions, 0 deletions