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authorEvan Cheng <evan.cheng@apple.com>2009-07-17 22:42:51 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-07-17 22:42:51 +0000
commit59959cd96673c2452ad006dc392ef8b5a278609c (patch)
tree85165821894301f2e4d4c3055cd730b4c88c87a7 /lib/CodeGen/StackSlotColoring.cpp
parentb4b53e5c13167925d6315a6f57c7b863e4e2b704 (diff)
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Fix pr4552. Stack slot coloring with register must take care not to generate illegal ams.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76258 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/StackSlotColoring.cpp')
-rw-r--r--lib/CodeGen/StackSlotColoring.cpp16
1 files changed, 16 insertions, 0 deletions
diff --git a/lib/CodeGen/StackSlotColoring.cpp b/lib/CodeGen/StackSlotColoring.cpp
index 582464478c..0d9ebbbeb8 100644
--- a/lib/CodeGen/StackSlotColoring.cpp
+++ b/lib/CodeGen/StackSlotColoring.cpp
@@ -503,6 +503,15 @@ bool StackSlotColoring::PropagateBackward(MachineBasicBlock::iterator MII,
if (Reg == OldReg) {
if (MO.isImplicit())
return false;
+
+ // Abort the use is actually a sub-register def. We don't have enough
+ // information to figure out if it is really legal.
+ if (MO.getSubReg() ||
+ TID.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
+ TID.getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+ TID.getOpcode() == TargetInstrInfo::SUBREG_TO_REG)
+ return false;
+
const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i);
if (RC && !RC->contains(NewReg))
return false;
@@ -561,12 +570,19 @@ bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII,
if (MO.isDef() || MO.isImplicit())
return false;
+ // Abort the use is actually a sub-register use. We don't have enough
+ // information to figure out if it is really legal.
+ if (MO.getSubReg() ||
+ TID.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)
+ return false;
+
const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i);
if (RC && !RC->contains(NewReg))
return false;
FoundUse = true;
if (MO.isKill())
FoundKill = true;
+
Uses.push_back(&MO);
} else if (TRI->regsOverlap(Reg, NewReg) ||
TRI->regsOverlap(Reg, OldReg))