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authorHal Finkel <hfinkel@anl.gov>2014-01-02 21:13:43 +0000
committerHal Finkel <hfinkel@anl.gov>2014-01-02 21:13:43 +0000
commitac8ba0c0fdf81b53acb12cd080ea591c69d0dfd0 (patch)
treefbd0278a31462f11284fcd6c114ace3c8298c6cb /lib/CodeGen/TargetLoweringBase.cpp
parent5f8e79e6d22cff558fde9f3d40844a9eceaf79ac (diff)
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Disable compare sinking in CodeGenPrepare when multiple condition registers are available
As noted in the comment above CodeGenPrepare::OptimizeInst, which aggressively sinks compares to reduce pressure on the condition register(s), for targets such as PowerPC with multiple condition registers, this may not be the right thing to do. This adds an HasMultipleConditionRegisters boolean to TLI, and CodeGenPrepare::OptimizeInst is skipped when HasMultipleConditionRegisters is true. This functionality will be used by the PowerPC backend in an upcoming commit. Especially when the PowerPC backend starts tracking individual condition register bits as separate allocatable entities (which will happen in this upcoming commit), this sinking from CodeGenPrepare::OptimizeInst is significantly suboptimial. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198354 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/TargetLoweringBase.cpp')
-rw-r--r--lib/CodeGen/TargetLoweringBase.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/CodeGen/TargetLoweringBase.cpp b/lib/CodeGen/TargetLoweringBase.cpp
index 7b1931d407..beaa9b9f74 100644
--- a/lib/CodeGen/TargetLoweringBase.cpp
+++ b/lib/CodeGen/TargetLoweringBase.cpp
@@ -672,6 +672,7 @@ TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
UseUnderscoreSetJmp = false;
UseUnderscoreLongJmp = false;
SelectIsExpensive = false;
+ HasMultipleConditionRegisters = false;
IntDivIsCheap = false;
Pow2DivIsCheap = false;
JumpIsExpensive = false;