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| author | Craig Topper <craig.topper@gmail.com> | 2014-04-04 05:16:06 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2014-04-04 05:16:06 +0000 |
| commit | 84f7f350c3f8e33c2143ff44aa0a3fbbfd82657f (patch) | |
| tree | 2558b3962c0fe30a89608ee7b2544277b62fb75f /lib/CodeGen/TargetRegisterInfo.cpp | |
| parent | 84c21b38a95235a4a2c71e0557c06d889fad6b4e (diff) | |
| download | llvm-84f7f350c3f8e33c2143ff44aa0a3fbbfd82657f.tar.gz llvm-84f7f350c3f8e33c2143ff44aa0a3fbbfd82657f.tar.bz2 llvm-84f7f350c3f8e33c2143ff44aa0a3fbbfd82657f.tar.xz | |
Make consistent use of MCPhysReg instead of uint16_t throughout the tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205610 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/TargetRegisterInfo.cpp')
| -rw-r--r-- | lib/CodeGen/TargetRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/TargetRegisterInfo.cpp b/lib/CodeGen/TargetRegisterInfo.cpp index 5a1524364b..b76028764c 100644 --- a/lib/CodeGen/TargetRegisterInfo.cpp +++ b/lib/CodeGen/TargetRegisterInfo.cpp @@ -130,7 +130,7 @@ TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R){ assert(RC->isAllocatable() && "invalid for nonallocatable sets"); - ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); + ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); for (unsigned i = 0; i != Order.size(); ++i) R.set(Order[i]); } |