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authorChris Lattner <sabre@nondot.org>2006-05-05 22:53:17 +0000
committerChris Lattner <sabre@nondot.org>2006-05-05 22:53:17 +0000
commit06afe070371c5bdcdc76d90d9e13f8532d9f95aa (patch)
tree9838f0eeabb92d5a9ffa749a38c786d41cf5e972 /lib/CodeGen
parentfe8babf689c624c53d03f5629324b049b5327a6e (diff)
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Shrink shifts when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28136 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 872242e46f..1175f527ac 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1615,6 +1615,18 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
DAG.getConstant(c1 + c2, N1.getValueType()));
}
+ // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
+ if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
+ // Shifting in all undef bits?
+ MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
+ if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
+ return DAG.getNode(ISD::UNDEF, VT);
+
+ SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
+ AddToWorkList(SmallShift.Val);
+ return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
+ }
+
// fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
if (N1C && N0.getOpcode() == ISD::CTLZ &&
N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {