summaryrefslogtreecommitdiff
path: root/lib/CodeGen
diff options
context:
space:
mode:
authorChris Lattner <sabre@nondot.org>2006-05-17 20:43:21 +0000
committerChris Lattner <sabre@nondot.org>2006-05-17 20:43:21 +0000
commit1b8daae71b0118b489cbecf2f1b8ed86b6bc8e57 (patch)
tree3625d2b5c9ec0ebbc350245bec26d2ca57998f0e /lib/CodeGen
parent2618d07765e94ca12c68c9db31e7843cc69d7178 (diff)
downloadllvm-1b8daae71b0118b489cbecf2f1b8ed86b6bc8e57.tar.gz
llvm-1b8daae71b0118b489cbecf2f1b8ed86b6bc8e57.tar.bz2
llvm-1b8daae71b0118b489cbecf2f1b8ed86b6bc8e57.tar.xz
Correct a previous patch which broke CodeGen/PowerPC/vec_call.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28364 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp23
1 files changed, 5 insertions, 18 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index e1d4d8e1e6..517b760854 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2551,25 +2551,12 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
// Figure out if there is a Packed type corresponding to this Vector
// type. If so, convert to the packed type.
- bool Supported = false;
MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
- if (TVT != MVT::Other) {
- // Handle copies from generic vectors to registers.
- MVT::ValueType PTyElementVT, PTyLegalElementVT;
- unsigned NE = getPackedTypeBreakdown(PTy, PTyElementVT,
- PTyLegalElementVT);
- // FIXME: handle NE > 1 cases.
- if (NE == 1) {
- // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
- Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
- DAG.getConstant(NumElems, MVT::i32),
- DAG.getValueType(getValueType(EltTy)));
- Ops.push_back(Op);
- Supported = true;
- }
- }
-
- if (!Supported) {
+ if (TVT != MVT::Other && isTypeLegal(TVT)) {
+ // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
+ Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
+ Ops.push_back(Op);
+ } else {
assert(0 && "Don't support illegal by-val vector call args yet!");
abort();
}