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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-06-25 10:02:21 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-06-25 10:02:21 +0000 |
| commit | 3e5582cc15639f7c908326a7c15b941fb3253a33 (patch) | |
| tree | 9c04cbc46280ed543efd6ff268a931ad2e0f5bf7 /lib/CodeGen | |
| parent | 97c856a6126f0853dd894cc5f78dfaa574c78540 (diff) | |
| download | llvm-3e5582cc15639f7c908326a7c15b941fb3253a33.tar.gz llvm-3e5582cc15639f7c908326a7c15b941fb3253a33.tar.bz2 llvm-3e5582cc15639f7c908326a7c15b941fb3253a33.tar.xz | |
[X86] Add target combine rule to select ADDSUB instructions from a build_vector
This patch teaches the backend how to combine a build_vector that implements
an 'addsub' between packed float vectors into a sequence of vector add
and vector sub followed by a VSELECT.
The new VSELECT is expected to be lowered into a BLENDI.
At ISel stage, the sequence 'vector add + vector sub + BLENDI' is
pattern-matched against ISel patterns added at r211427 to select
'addsub' instructions.
Added three more ISel patterns for ADDSUB.
Added test sse3-avx-addsub-2.ll to verify that we correctly emit 'addsub'
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211679 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
0 files changed, 0 insertions, 0 deletions