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| author | Kevin Qin <Kevin.Qin@arm.com> | 2013-12-30 02:05:13 +0000 |
|---|---|---|
| committer | Kevin Qin <Kevin.Qin@arm.com> | 2013-12-30 02:05:13 +0000 |
| commit | 3f8f3c9feb2e10e1f936dee23973b56bc361722d (patch) | |
| tree | e5edea256fec094a9d832f297210f3394ce5364c /lib/CodeGen | |
| parent | 3796015b5bcaa1a27ff1a6816a8c87bd58d8629b (diff) | |
| download | llvm-3f8f3c9feb2e10e1f936dee23973b56bc361722d.tar.gz llvm-3f8f3c9feb2e10e1f936dee23973b56bc361722d.tar.bz2 llvm-3f8f3c9feb2e10e1f936dee23973b56bc361722d.tar.xz | |
Fix a bug in DAGcombiner about zero-extend after setcc.
For AArch64 backend, if DAGCombiner see "sext(setcc)", it will
combine them together to a single setcc with extended value type.
Then if it see "zext(setcc)", it assumes setcc is Vxi1, and try to
create "(and (vsetcc), (1, 1, ...)". While setcc isn't Vxi1,
DAGcombiner will create wrong node and get wrong code emitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198190 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 68d0521e76..3b87922b78 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4970,7 +4970,8 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { } if (N0.getOpcode() == ISD::SETCC) { - if (!LegalOperations && VT.isVector()) { + if (!LegalOperations && VT.isVector() && + N0.getValueType().getVectorElementType() == MVT::i1) { // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. // Only do this before legalize for now. EVT N0VT = N0.getOperand(0).getValueType(); |