s/Method/Function

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2336 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 20 insertions, 20 deletions

diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index adc8903541..4c2a28c788 100644
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -9,7 +9,7 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
 #include "llvm/CodeGen/MachineCodeForMethod.h"
-#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h" // FIXME: Remove when AnalysisUsage sets can be symbolic!
+#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/BasicBlock.h"
 #include "llvm/Instruction.h"
@@ -1487,7 +1487,7 @@ namespace {
   
     // getAnalysisUsage - We use LiveVarInfo...
     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
-      AU.addRequired(MethodLiveVarInfo::ID);
+      AU.addRequired(FunctionLiveVarInfo::ID);
     }
     
     bool runOnFunction(Function *F);
@@ -1521,7 +1521,7 @@ InstructionSchedulingWithSSA::runOnFunction(Function *M)
         cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
       
       // expensive!
-      SchedPriorities schedPrio(M, graph,getAnalysis<MethodLiveVarInfo>());
+      SchedPriorities schedPrio(M, graph,getAnalysis<FunctionLiveVarInfo>());
       SchedulingManager S(target, graph, schedPrio);
           
       ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
diff --git a/lib/CodeGen/InstrSched/SchedPriorities.cpp b/lib/CodeGen/InstrSched/SchedPriorities.cpp
index 02e50c0cc7..a4480e8865 100644
--- a/lib/CodeGen/InstrSched/SchedPriorities.cpp
+++ b/lib/CodeGen/InstrSched/SchedPriorities.cpp
@@ -19,14 +19,14 @@
 //**************************************************************************/
 
 #include "SchedPriorities.h"
-#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
+#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
 #include "llvm/Support/CFG.h"
 #include "Support/PostOrderIterator.h"
 #include <iostream>
 using std::cerr;
 
 SchedPriorities::SchedPriorities(const Function *, const SchedGraph *G,
-                                 MethodLiveVarInfo &LVI)
+                                 FunctionLiveVarInfo &LVI)
   : curTime(0), graph(G), methodLiveVarInfo(LVI),
     nodeDelayVec(G->getNumNodes(), INVALID_LATENCY), // make errors obvious
     earliestForNode(G->getNumNodes(), 0),
@@ -266,7 +266,7 @@ SchedPriorities::findSetWithMaxDelay(std::vector<candIndex>& mcands,
 
 
 bool
-SchedPriorities::instructionHasLastUse(MethodLiveVarInfo& methodLiveVarInfo,
+SchedPriorities::instructionHasLastUse(FunctionLiveVarInfo &LVI,
 				       const SchedGraphNode* graphNode) {
   const MachineInstr *MI = graphNode->getMachineInstr();
   
@@ -278,7 +278,7 @@ SchedPriorities::instructionHasLastUse(MethodLiveVarInfo& methodLiveVarInfo,
   // else check if instruction is a last use and save it in the hash_map
   bool hasLastUse = false;
   const BasicBlock* bb = graphNode->getBB();
-  const ValueSet &LVs = methodLiveVarInfo.getLiveVarSetBeforeMInst(MI, bb);
+  const ValueSet &LVs = LVI.getLiveVarSetBeforeMInst(MI, bb);
   
   for (MachineInstr::const_val_op_iterator OI = MI->begin(), OE = MI->end();
        OI != OE; ++OI)
diff --git a/lib/CodeGen/InstrSched/SchedPriorities.h b/lib/CodeGen/InstrSched/SchedPriorities.h
index c76beadcb5..3f087d5224 100644
--- a/lib/CodeGen/InstrSched/SchedPriorities.h
+++ b/lib/CodeGen/InstrSched/SchedPriorities.h
@@ -31,7 +31,7 @@
 class Function;
 class MachineInstr;
 class SchedulingManager;
-class MethodLiveVarInfo;
+class FunctionLiveVarInfo;
 
 //---------------------------------------------------------------------------
 // Debug option levels for instruction scheduling
@@ -127,7 +127,7 @@ private:
 class SchedPriorities: public NonCopyable {
 public:
   SchedPriorities(const Function *F, const SchedGraph *G,
-                  MethodLiveVarInfo &LVI);
+                  FunctionLiveVarInfo &LVI);
                   
   
   // This must be called before scheduling begins.
@@ -157,7 +157,7 @@ private:
 private:
   cycles_t curTime;
   const SchedGraph* graph;
-  MethodLiveVarInfo &methodLiveVarInfo;
+  FunctionLiveVarInfo &methodLiveVarInfo;
   std::hash_map<const MachineInstr*, bool> lastUseMap;
   std::vector<cycles_t> nodeDelayVec;
   std::vector<cycles_t> earliestForNode;
@@ -180,7 +180,7 @@ private:
   
   void		initializeReadyHeap	(const SchedGraph* graph);
   
-  bool		instructionHasLastUse	(MethodLiveVarInfo& methodLiveVarInfo,
+  bool		instructionHasLastUse	(FunctionLiveVarInfo& LVI,
 					 const SchedGraphNode* graphNode);
   
   // NOTE: The next two return references to the actual vector entries.
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index c22ede96b3..4f12d697b1 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -14,7 +14,7 @@
 #include "llvm/CodeGen/PhyRegAlloc.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineCodeForMethod.h"
-#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
+#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
 #include "llvm/Analysis/LoopInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/MachineFrameInfo.h"
@@ -50,7 +50,7 @@ namespace {
         cerr << "\n******************** Function "<< F->getName()
              << " ********************\n";
       
-      PhyRegAlloc PRA(F, Target, &getAnalysis<MethodLiveVarInfo>(),
+      PhyRegAlloc PRA(F, Target, &getAnalysis<FunctionLiveVarInfo>(),
                       &getAnalysis<cfg::LoopInfo>());
       PRA.allocateRegisters();
       
@@ -60,7 +60,7 @@ namespace {
 
     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
       AU.addRequired(cfg::LoopInfo::ID);
-      AU.addRequired(MethodLiveVarInfo::ID);
+      AU.addRequired(FunctionLiveVarInfo::ID);
     }
   };
 }
@@ -74,7 +74,7 @@ Pass *getRegisterAllocator(TargetMachine &T) {
 //----------------------------------------------------------------------------
 PhyRegAlloc::PhyRegAlloc(Function *F, 
 			 const TargetMachine& tm, 
-			 MethodLiveVarInfo *Lvi,
+			 FunctionLiveVarInfo *Lvi,
                          cfg::LoopInfo *LDC) 
                        :  TM(tm), Meth(F),
                           mcInfo(MachineCodeForMethod::get(F)),
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.h b/lib/CodeGen/RegAlloc/PhyRegAlloc.h
index 5922497f11..5cc01c6765 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.h
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.h
@@ -17,13 +17,13 @@
 
    Register allocation must be done  as:	
 
-      MethodLiveVarInfo LVI(*MethodI );           // compute LV info
+      FunctionLiveVarInfo LVI(*FunctionI );           // compute LV info
       LVI.analyze();
 
       TargetMachine &target = ....	                        
 
 
-      PhyRegAlloc PRA(*MethodI, target, &LVI);     // allocate regs
+      PhyRegAlloc PRA(*FunctionI, target, &LVI);     // allocate regs
       PRA.allocateRegisters();
 */ 
 
@@ -35,7 +35,7 @@
 #include <deque>
 class MachineCodeForMethod;
 class MachineRegInfo;
-class MethodLiveVarInfo;
+class FunctionLiveVarInfo;
 class MachineInstr;
 namespace cfg { class LoopInfo; }
 
@@ -70,7 +70,7 @@ class PhyRegAlloc: public NonCopyable {
   const TargetMachine &TM;              // target machine
   const Function *Meth;                 // name of the function we work on
   MachineCodeForMethod &mcInfo;         // descriptor for method's native code
-  MethodLiveVarInfo *const LVI;         // LV information for this method 
+  FunctionLiveVarInfo *const LVI;         // LV information for this method 
                                         // (already computed for BBs) 
   LiveRangeInfo LRI;                    // LR info  (will be computed)
   const MachineRegInfo &MRI;            // Machine Register information
@@ -84,7 +84,7 @@ class PhyRegAlloc: public NonCopyable {
                                         // currently not used
 
 public:
-  PhyRegAlloc(Function *F, const TargetMachine& TM, MethodLiveVarInfo *Lvi,
+  PhyRegAlloc(Function *F, const TargetMachine& TM, FunctionLiveVarInfo *Lvi,
               cfg::LoopInfo *LoopDepthCalc);
   ~PhyRegAlloc();