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author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-06-21 01:31:15 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-06-21 01:31:15 +0000 |
commit | 5d0ff9c9289fc4f9e99c7b27b7c8b42597cd8765 (patch) | |
tree | 50c46c9d176b6b63beb19e17323c1cd157684df0 /lib/CodeGen | |
parent | 9222a2375f1f2cb9528c6d9b32238f6bac434d94 (diff) | |
download | llvm-5d0ff9c9289fc4f9e99c7b27b7c8b42597cd8765.tar.gz llvm-5d0ff9c9289fc4f9e99c7b27b7c8b42597cd8765.tar.bz2 llvm-5d0ff9c9289fc4f9e99c7b27b7c8b42597cd8765.tar.xz |
[X86] Add ISel patterns to select SSE3/AVX ADDSUB instructions.
This patch adds ISel patterns to select SSE3/AVX ADDSUB instructions
from a sequence of "vadd + vsub + blend".
Example:
///
typedef float float4 __attribute__((ext_vector_type(4)));
float4 foo(float4 A, float4 B) {
float4 X = A - B;
float4 Y = A + B;
return (float4){X[0], Y[1], X[2], Y[3]};
}
///
Before this patch, (with flag -mcpu=corei7) llc produced the following
assembly sequence:
movaps %xmm0, %xmm2
addps %xmm1, %xmm2
subps %xmm1, %xmm0
blendps $10, %xmm2, %xmm0
With this patch, we now get a single
addsubps %xmm1, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211427 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
0 files changed, 0 insertions, 0 deletions