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| author | Chris Lattner <sabre@nondot.org> | 2002-05-20 21:39:10 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2002-05-20 21:39:10 +0000 |
| commit | ad86b74bafe3f25000d0172fda4479c0a305ff3a (patch) | |
| tree | e278b95eca611d7be3dcc44799010b3127ca4172 /lib/CodeGen | |
| parent | 39fd659d683592df13ccfa39f1825b1173a9ff04 (diff) | |
| download | llvm-ad86b74bafe3f25000d0172fda4479c0a305ff3a.tar.gz llvm-ad86b74bafe3f25000d0172fda4479c0a305ff3a.tar.bz2 llvm-ad86b74bafe3f25000d0172fda4479c0a305ff3a.tar.xz | |
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2676 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/InstrSched/InstrScheduling.cpp | 2 | ||||
| -rw-r--r-- | lib/CodeGen/InstrSelection/InstrSelection.cpp | 2 | ||||
| -rw-r--r-- | lib/CodeGen/RegAlloc/PhyRegAlloc.cpp | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp index d219ef6b6d..0a6d1ce353 100644 --- a/lib/CodeGen/InstrSched/InstrScheduling.cpp +++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp @@ -19,7 +19,7 @@ using std::vector; //************************* External Data Types *****************************/ -cl::Enum<enum SchedDebugLevel_t> SchedDebugLevel("dsched", cl::NoFlags, +cl::Enum<enum SchedDebugLevel_t> SchedDebugLevel("dsched", cl::Hidden, "enable instruction scheduling debugging information", clEnumValN(Sched_NoDebugInfo, "n", "disable debug output"), clEnumValN(Sched_Disable, "off", "disable instruction scheduling"), diff --git a/lib/CodeGen/InstrSelection/InstrSelection.cpp b/lib/CodeGen/InstrSelection/InstrSelection.cpp index 0776b15974..614c5f6773 100644 --- a/lib/CodeGen/InstrSelection/InstrSelection.cpp +++ b/lib/CodeGen/InstrSelection/InstrSelection.cpp @@ -39,7 +39,7 @@ enum SelectDebugLevel_t { }; // Enable Debug Options to be specified on the command line -cl::Enum<enum SelectDebugLevel_t> SelectDebugLevel("dselect", cl::NoFlags, +cl::Enum<enum SelectDebugLevel_t> SelectDebugLevel("dselect", cl::Hidden, "enable instruction selection debugging information", clEnumValN(Select_NoDebugInfo, "n", "disable debug output"), clEnumValN(Select_PrintMachineCode, "y", "print generated machine code"), diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp index 785a12411a..ab9b1a7b17 100644 --- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp +++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp @@ -32,7 +32,7 @@ using std::cerr; // ***TODO: There are several places we add instructions. Validate the order // of adding these instructions. -cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags, +cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::Hidden, "enable register allocation debugging information", clEnumValN(RA_DEBUG_None , "n", "disable debug output"), clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"), |