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| author | Evan Cheng <evan.cheng@apple.com> | 2006-05-26 23:13:20 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-05-26 23:13:20 +0000 |
| commit | d61c4820c9e39500a67bec4d6cfe521a833afdcc (patch) | |
| tree | a33550d65792c35eb28a132cec2add2a36101b1b /lib/CodeGen | |
| parent | 6848be1a27e08a89dcd4dd69f746471a608012cd (diff) | |
| download | llvm-d61c4820c9e39500a67bec4d6cfe521a833afdcc.tar.gz llvm-d61c4820c9e39500a67bec4d6cfe521a833afdcc.tar.bz2 llvm-d61c4820c9e39500a67bec4d6cfe521a833afdcc.tar.xz | |
Make CALL node consistent with RET node. Signness of value has type MVT::i32
instead of MVT::i1. Either is fine except MVT::i32 is probably a legal type
for most (if not all) platforms while MVT::i1 is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28511 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index b0af5441dd..0365e904f3 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2515,7 +2515,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, default: assert(0 && "Unknown type action!"); case Legal: Ops.push_back(Op); - Ops.push_back(DAG.getConstant(isSigned, MVT::i1)); + Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); break; case Promote: if (MVT::isInteger(VT)) { @@ -2526,7 +2526,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); } Ops.push_back(Op); - Ops.push_back(DAG.getConstant(isSigned, MVT::i1)); + Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); break; case Expand: if (VT != MVT::Vector) { @@ -2544,9 +2544,9 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, std::swap(Lo, Hi); Ops.push_back(Lo); - Ops.push_back(DAG.getConstant(isSigned, MVT::i1)); + Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); Ops.push_back(Hi); - Ops.push_back(DAG.getConstant(isSigned, MVT::i1)); + Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); } else { // Value scalarized into many values. Unimp for now. assert(0 && "Cannot expand i64 -> i16 yet!"); @@ -2565,7 +2565,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type. Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op); Ops.push_back(Op); - Ops.push_back(DAG.getConstant(isSigned, MVT::i1)); + Ops.push_back(DAG.getConstant(isSigned, MVT::i32)); } else { assert(0 && "Don't support illegal by-val vector call args yet!"); abort(); |