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| author | Chris Lattner <sabre@nondot.org> | 2006-05-06 09:30:03 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-05-06 09:30:03 +0000 |
| commit | ee4ea923589a2556ff85edbaf444d9575050613a (patch) | |
| tree | 3386cf0cb078122fd5b4019b21a734f4ae119a2b /lib/CodeGen | |
| parent | 5c3e21d68726dbfc313d8af3d320b0a6b3eeac36 (diff) | |
| download | llvm-ee4ea923589a2556ff85edbaf444d9575050613a.tar.gz llvm-ee4ea923589a2556ff85edbaf444d9575050613a.tar.bz2 llvm-ee4ea923589a2556ff85edbaf444d9575050613a.tar.xz | |
Use the new TargetLowering::ComputeNumSignBits method to eliminate
sign_extend_inreg operations. Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:
short test(short X, short x) {
int Y = X+x;
return (Y >> 1);
}
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
into:
_test:
add r2, r3, r4
srawi r3, r2, 1
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test:
add r2, r3, r4
srawi r2, r2, 1
extsh r3, r2
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r2, r2, 1
extsh r3, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28146 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index b967855eee..16ce87a536 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1937,6 +1937,11 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); } + + // If the input is already sign extended, just drop the extend. + if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) + return N0; + // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { @@ -1947,11 +1952,6 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); } - // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) - if (N0.getOpcode() == ISD::AssertSext && - cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { - return N0; - } // fold (sext_in_reg (sextload x)) -> (sextload x) if (N0.getOpcode() == ISD::SEXTLOAD && cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { |