* Rename MethodPass class to FunctionPass

  - Rename runOnMethod to runOnFunction
* Transform getAnalysisUsageInfo into getAnalysisUsage
  - Method is now const
  - It now takes one AnalysisUsage object to fill in instead of 3 vectors
    to fill in
  - Pass's now specify which other passes they _preserve_ not which ones
    they modify (be conservative!)
  - A pass can specify that it preserves all analyses (because it never
    modifies the underlying program)
* s/Method/Function/g in other random places as well


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2333 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 14 insertions, 22 deletions

diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index f10bf3c412..adc8903541 100644
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -1480,26 +1480,23 @@ instrIsFeasible(const SchedulingManager& S,
 //---------------------------------------------------------------------------
 
 namespace {
-  class InstructionSchedulingWithSSA : public MethodPass {
+  class InstructionSchedulingWithSSA : public FunctionPass {
     const TargetMachine ⌖
   public:
     inline InstructionSchedulingWithSSA(const TargetMachine &T) : target(T) {}
   
-    // getAnalysisUsageInfo - We use LiveVarInfo...
-    virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires,
-                                      Pass::AnalysisSet &Destroyed,
-                                      Pass::AnalysisSet &Provided) {
-      Requires.push_back(MethodLiveVarInfo::ID);
-      Destroyed.push_back(MethodLiveVarInfo::ID);
+    // getAnalysisUsage - We use LiveVarInfo...
+    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+      AU.addRequired(MethodLiveVarInfo::ID);
     }
     
-    bool runOnMethod(Function *F);
+    bool runOnFunction(Function *F);
   };
 } // end anonymous namespace
 
 
 bool
-InstructionSchedulingWithSSA::runOnMethod(Function *M)
+InstructionSchedulingWithSSA::runOnFunction(Function *M)
 {
   if (SchedDebugLevel == Sched_Disable)
     return false;
@@ -1544,8 +1541,6 @@ InstructionSchedulingWithSSA::runOnMethod(Function *M)
 }
 
 
-MethodPass*
-createInstructionSchedulingWithSSAPass(const TargetMachine &tgt)
-{
+Pass *createInstructionSchedulingWithSSAPass(const TargetMachine &tgt) {
   return new InstructionSchedulingWithSSA(tgt);
 }
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 0b680ab9e4..c22ede96b3 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -40,14 +40,14 @@ cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
 // RegisterAllocation pass front end...
 //----------------------------------------------------------------------------
 namespace {
-  class RegisterAllocator : public MethodPass {
+  class RegisterAllocator : public FunctionPass {
     TargetMachine &Target;
   public:
     inline RegisterAllocator(TargetMachine &T) : Target(T) {}
     
-    bool runOnMethod(Function *F) {
+    bool runOnFunction(Function *F) {
       if (DEBUG_RA)
-        cerr << "\n******************** Method "<< F->getName()
+        cerr << "\n******************** Function "<< F->getName()
              << " ********************\n";
       
       PhyRegAlloc PRA(F, Target, &getAnalysis<MethodLiveVarInfo>(),
@@ -58,17 +58,14 @@ namespace {
       return false;
     }
 
-    virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires,
-                                      Pass::AnalysisSet &Destroyed,
-                                      Pass::AnalysisSet &Provided) {
-      Requires.push_back(cfg::LoopInfo::ID);
-      Requires.push_back(MethodLiveVarInfo::ID);
-      Destroyed.push_back(MethodLiveVarInfo::ID);
+    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+      AU.addRequired(cfg::LoopInfo::ID);
+      AU.addRequired(MethodLiveVarInfo::ID);
     }
   };
 }
 
-MethodPass *getRegisterAllocator(TargetMachine &T) {
+Pass *getRegisterAllocator(TargetMachine &T) {
   return new RegisterAllocator(T);
 }