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| author | Tim Northover <tnorthover@apple.com> | 2014-03-11 10:48:52 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-03-11 10:48:52 +0000 |
| commit | ca396e391e13d417605ebed06780d92c88f14a6b (patch) | |
| tree | a984bbd50ef52c0ad3f0fd66b81d1021b072d16c /lib/IR/AsmWriter.h | |
| parent | fb411c8b8ce42689d42b0d8e3a871d81f86a7298 (diff) | |
| download | llvm-ca396e391e13d417605ebed06780d92c88f14a6b.tar.gz llvm-ca396e391e13d417605ebed06780d92c88f14a6b.tar.bz2 llvm-ca396e391e13d417605ebed06780d92c88f14a6b.tar.xz | |
IR: add a second ordering operand to cmpxhg for failure
The syntax for "cmpxchg" should now look something like:
cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic
where the second ordering argument gives the required semantics in the case
that no exchange takes place. It should be no stronger than the first ordering
constraint and cannot be either "release" or "acq_rel" (since no store will
have taken place).
rdar://problem/15996804
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203559 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/IR/AsmWriter.h')
| -rw-r--r-- | lib/IR/AsmWriter.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/IR/AsmWriter.h b/lib/IR/AsmWriter.h index 222d3a490f..b4ce6de10d 100644 --- a/lib/IR/AsmWriter.h +++ b/lib/IR/AsmWriter.h @@ -90,6 +90,9 @@ public: void writeOperand(const Value *Op, bool PrintType); void writeParamOperand(const Value *Operand, AttributeSet Attrs,unsigned Idx); void writeAtomic(AtomicOrdering Ordering, SynchronizationScope SynchScope); + void writeAtomicCmpXchg(AtomicOrdering SuccessOrdering, + AtomicOrdering FailureOrdering, + SynchronizationScope SynchScope); void writeAllMDNodes(); void writeMDNode(unsigned Slot, const MDNode *Node); |