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| author | Tim Northover <tnorthover@apple.com> | 2014-06-03 13:54:53 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-06-03 13:54:53 +0000 |
| commit | 1410a2c9069ef174934e245b86e776dc9720824e (patch) | |
| tree | 9ce59672526ca4fed6faec1d95d451c07223a65b /lib/Target/AArch64/AArch64ISelLowering.cpp | |
| parent | e9b2cf3456e2ecc04e63f9ea03cfc47ffbb12614 (diff) | |
| download | llvm-1410a2c9069ef174934e245b86e776dc9720824e.tar.gz llvm-1410a2c9069ef174934e245b86e776dc9720824e.tar.bz2 llvm-1410a2c9069ef174934e245b86e776dc9720824e.tar.xz | |
AArch64: mark small types (i1, i8, i16) as promoted
This means the output of LowerFormalArguments returns a lowered
SDValue with the correct type (expected in SelectionDAGBuilder).
Without this, an assertion under a DEBUG macro triggers when those
types are passed on the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210102 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64ISelLowering.cpp')
| -rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.cpp | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 4bc22c338e..4ce0362f4f 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1781,21 +1781,21 @@ SDValue AArch64TargetLowering::LowerFormalArguments( switch (VA.getLocInfo()) { default: break; + case CCValAssign::BCvt: + MemVT = VA.getLocVT(); + break; case CCValAssign::SExt: ExtType = ISD::SEXTLOAD; - MemVT = VA.getLocVT(); break; case CCValAssign::ZExt: ExtType = ISD::ZEXTLOAD; - MemVT = VA.getLocVT(); break; case CCValAssign::AExt: ExtType = ISD::EXTLOAD; - MemVT = VA.getLocVT(); break; } - ArgValue = DAG.getExtLoad(ExtType, DL, VA.getValVT(), Chain, FIN, + ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN, MachinePointerInfo::getFixedStack(FI), MemVT, false, false, false, 0); @@ -2346,11 +2346,9 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already // promoted to a legal register type i32, we should truncate Arg back to // i1/i8/i16. - if (Arg.getValueType().isSimple() && - Arg.getValueType().getSimpleVT() == MVT::i32 && - (VA.getLocVT() == MVT::i1 || VA.getLocVT() == MVT::i8 || - VA.getLocVT() == MVT::i16)) - Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getLocVT(), Arg); + if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 || + VA.getValVT() == MVT::i16) + Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); SDValue Store = DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0); |