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author | Renato Golin <renato.golin@linaro.org> | 2014-05-06 16:51:25 +0000 |
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committer | Renato Golin <renato.golin@linaro.org> | 2014-05-06 16:51:25 +0000 |
commit | 22f779d1fd0d7a7e878a3c28bc5d9910ae655df3 (patch) | |
tree | 272b3978eb4e467ad4854aa00a03dda055046001 /lib/Target/AArch64/AArch64ISelLowering.cpp | |
parent | b8894488415a81bb6bdaf9851acacc93a4e7cfe2 (diff) | |
download | llvm-22f779d1fd0d7a7e878a3c28bc5d9910ae655df3.tar.gz llvm-22f779d1fd0d7a7e878a3c28bc5d9910ae655df3.tar.bz2 llvm-22f779d1fd0d7a7e878a3c28bc5d9910ae655df3.tar.xz |
Implememting named register intrinsics
This patch implements the infrastructure to use named register constructs in
programs that need access to specific registers (bare metal, kernels, etc).
So far, only the stack pointer is supported as a technology preview, but as it
is, the intrinsic can already support all non-allocatable registers from any
architecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208104 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64ISelLowering.cpp')
-rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 5ad2036d51..a016e6e485 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -15,6 +15,7 @@ #include "AArch64.h" #include "AArch64ISelLowering.h" #include "AArch64MachineFunctionInfo.h" +#include "AArch64Subtarget.h" #include "AArch64TargetMachine.h" #include "AArch64TargetObjectFile.h" #include "Utils/AArch64BaseInfo.h" @@ -2406,6 +2407,17 @@ SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) return FrameAddr; } +// FIXME? Maybe this could be a TableGen attribute on some registers and +// this table could be generated automatically from RegInfo. +unsigned AArch64TargetLowering::getRegisterByName(const char* RegName) const { + unsigned Reg = StringSwitch<unsigned>(RegName) + .Case("sp", AArch64::XSP) + .Default(0); + if (Reg) + return Reg; + report_fatal_error("Invalid register name global variable"); +} + SDValue AArch64TargetLowering::LowerGlobalAddressELFLarge(SDValue Op, SelectionDAG &DAG) const { |