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authorHao Liu <Hao.Liu@arm.com>2014-01-07 10:50:43 +0000
committerHao Liu <Hao.Liu@arm.com>2014-01-07 10:50:43 +0000
commit1a080cef909279240f14ebfb8ec19db9c038cbfb (patch)
tree5a6d6f8646a49b3deba38343746e6c9fc150bd49 /lib/Target/AArch64/AArch64RegisterInfo.cpp
parentbba676f3fee988c09c23172aa09eb6a363d9f473 (diff)
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[AArch64]Add support to spill/fill D tuples such as DPair/DTriple/DQuad. There is no test cases for D tuple as the original test cases are too large. As the spill/fill of the D tuple is similar to the Q tuple, the correctness can be guaranteed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198684 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64RegisterInfo.cpp')
-rw-r--r--lib/Target/AArch64/AArch64RegisterInfo.cpp5
1 files changed, 4 insertions, 1 deletions
diff --git a/lib/Target/AArch64/AArch64RegisterInfo.cpp b/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 618f6fb928..973faf7363 100644
--- a/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -77,7 +77,10 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
}
static bool hasFrameOffset(int opcode) {
- return opcode != AArch64::LD1x2_16B && opcode != AArch64::LD1x3_16B &&
+ return opcode != AArch64::LD1x2_8B && opcode != AArch64::LD1x3_8B &&
+ opcode != AArch64::LD1x4_8B && opcode != AArch64::ST1x2_8B &&
+ opcode != AArch64::ST1x3_8B && opcode != AArch64::ST1x4_8B &&
+ opcode != AArch64::LD1x2_16B && opcode != AArch64::LD1x3_16B &&
opcode != AArch64::LD1x4_16B && opcode != AArch64::ST1x2_16B &&
opcode != AArch64::ST1x3_16B && opcode != AArch64::ST1x4_16B;
}