diff options
author | Kevin Qin <Kevin.Qin@arm.com> | 2013-11-29 01:29:16 +0000 |
---|---|---|
committer | Kevin Qin <Kevin.Qin@arm.com> | 2013-11-29 01:29:16 +0000 |
commit | 922419232152567ef4f574c642fa1b7da19aa49d (patch) | |
tree | 649309b18f61dc6223ecab5580e7cf7e8735071e /lib/Target/AArch64/Disassembler | |
parent | e9f8ce8cde3767b54751e95ddb6ed56b429ec138 (diff) | |
download | llvm-922419232152567ef4f574c642fa1b7da19aa49d.tar.gz llvm-922419232152567ef4f574c642fa1b7da19aa49d.tar.bz2 llvm-922419232152567ef4f574c642fa1b7da19aa49d.tar.xz |
[AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195936 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/Disassembler')
-rw-r--r-- | lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 1f70a3d32c..be4d7f22b2 100644 --- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -238,6 +238,10 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + static bool Check(DecodeStatus &Out, DecodeStatus In); #include "AArch64GenDisassemblerTables.inc" @@ -1534,3 +1538,35 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, return MCDisassembler::Success; } + +static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) { + unsigned Rd = fieldFromInstruction(Insn, 0, 5); + unsigned Rn = fieldFromInstruction(Insn, 5, 5); + unsigned size = fieldFromInstruction(Insn, 22, 2); + unsigned Q = fieldFromInstruction(Insn, 30, 1); + + DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); + + if(Q) + DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); + else + DecodeFPR64RegisterClass(Inst, Rn, Address, Decoder); + + switch (size) { + case 0: + Inst.addOperand(MCOperand::CreateImm(8)); + break; + case 1: + Inst.addOperand(MCOperand::CreateImm(16)); + break; + case 2: + Inst.addOperand(MCOperand::CreateImm(32)); + break; + default : + return MCDisassembler::Fail; + } + return MCDisassembler::Success; +} + |