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| author | Tim Northover <Tim.Northover@arm.com> | 2013-02-05 13:24:56 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2013-02-05 13:24:56 +0000 |
| commit | dfe076af9879eb68a7b8331f9c02eecf563d85be (patch) | |
| tree | e1c1993543cc51da36b9cfc99ca0e7104a28ef33 /lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp | |
| parent | 19254c49a8752fe8c6fa648a6eb29f20a1f62c8b (diff) | |
| download | llvm-dfe076af9879eb68a7b8331f9c02eecf563d85be.tar.gz llvm-dfe076af9879eb68a7b8331f9c02eecf563d85be.tar.bz2 llvm-dfe076af9879eb68a7b8331f9c02eecf563d85be.tar.xz | |
Fix formatting in AArch64 backend.
This should fix three purely whitespace issues:
+ 80 column violations.
+ Tab characters.
+ TableGen brace placement.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174370 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp')
| -rw-r--r-- | lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp | 134 |
1 files changed, 67 insertions, 67 deletions
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp index a206fd17f5..5d5e38e6f7 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp @@ -94,73 +94,73 @@ public: // This table *must* be in the order that the fixup_* kinds are defined in // AArch64FixupKinds.h. // -// Name Offset (bits) Size (bits) Flags - { "fixup_a64_ld_prel", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_a64_adr_prel", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_a64_adr_prel_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_a64_add_lo12", 0, 32, 0 }, - { "fixup_a64_ldst8_lo12", 0, 32, 0 }, - { "fixup_a64_ldst16_lo12", 0, 32, 0 }, - { "fixup_a64_ldst32_lo12", 0, 32, 0 }, - { "fixup_a64_ldst64_lo12", 0, 32, 0 }, - { "fixup_a64_ldst128_lo12", 0, 32, 0 }, - { "fixup_a64_tstbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_a64_condbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_a64_uncondbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_a64_call", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_a64_movw_uabs_g0", 0, 32, 0 }, - { "fixup_a64_movw_uabs_g0_nc", 0, 32, 0 }, - { "fixup_a64_movw_uabs_g1", 0, 32, 0 }, - { "fixup_a64_movw_uabs_g1_nc", 0, 32, 0 }, - { "fixup_a64_movw_uabs_g2", 0, 32, 0 }, - { "fixup_a64_movw_uabs_g2_nc", 0, 32, 0 }, - { "fixup_a64_movw_uabs_g3", 0, 32, 0 }, - { "fixup_a64_movw_sabs_g0", 0, 32, 0 }, - { "fixup_a64_movw_sabs_g1", 0, 32, 0 }, - { "fixup_a64_movw_sabs_g2", 0, 32, 0 }, - { "fixup_a64_adr_prel_got_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_a64_ld64_got_lo12_nc", 0, 32, 0 }, - { "fixup_a64_movw_dtprel_g2", 0, 32, 0 }, - { "fixup_a64_movw_dtprel_g1", 0, 32, 0 }, - { "fixup_a64_movw_dtprel_g1_nc", 0, 32, 0 }, - { "fixup_a64_movw_dtprel_g0", 0, 32, 0 }, - { "fixup_a64_movw_dtprel_g0_nc", 0, 32, 0 }, - { "fixup_a64_add_dtprel_hi12", 0, 32, 0 }, - { "fixup_a64_add_dtprel_lo12", 0, 32, 0 }, - { "fixup_a64_add_dtprel_lo12_nc", 0, 32, 0 }, - { "fixup_a64_ldst8_dtprel_lo12", 0, 32, 0 }, - { "fixup_a64_ldst8_dtprel_lo12_nc", 0, 32, 0 }, - { "fixup_a64_ldst16_dtprel_lo12", 0, 32, 0 }, - { "fixup_a64_ldst16_dtprel_lo12_nc", 0, 32, 0 }, - { "fixup_a64_ldst32_dtprel_lo12", 0, 32, 0 }, - { "fixup_a64_ldst32_dtprel_lo12_nc", 0, 32, 0 }, - { "fixup_a64_ldst64_dtprel_lo12", 0, 32, 0 }, - { "fixup_a64_ldst64_dtprel_lo12_nc", 0, 32, 0 }, - { "fixup_a64_movw_gottprel_g1", 0, 32, 0 }, - { "fixup_a64_movw_gottprel_g0_nc", 0, 32, 0 }, - { "fixup_a64_adr_gottprel_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_a64_ld64_gottprel_lo12_nc", 0, 32, 0 }, - { "fixup_a64_ld_gottprel_prel19", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_a64_movw_tprel_g2", 0, 32, 0 }, - { "fixup_a64_movw_tprel_g1", 0, 32, 0 }, - { "fixup_a64_movw_tprel_g1_nc", 0, 32, 0 }, - { "fixup_a64_movw_tprel_g0", 0, 32, 0 }, - { "fixup_a64_movw_tprel_g0_nc", 0, 32, 0 }, - { "fixup_a64_add_tprel_hi12", 0, 32, 0 }, - { "fixup_a64_add_tprel_lo12", 0, 32, 0 }, - { "fixup_a64_add_tprel_lo12_nc", 0, 32, 0 }, - { "fixup_a64_ldst8_tprel_lo12", 0, 32, 0 }, - { "fixup_a64_ldst8_tprel_lo12_nc", 0, 32, 0 }, - { "fixup_a64_ldst16_tprel_lo12", 0, 32, 0 }, - { "fixup_a64_ldst16_tprel_lo12_nc", 0, 32, 0 }, - { "fixup_a64_ldst32_tprel_lo12", 0, 32, 0 }, - { "fixup_a64_ldst32_tprel_lo12_nc", 0, 32, 0 }, - { "fixup_a64_ldst64_tprel_lo12", 0, 32, 0 }, - { "fixup_a64_ldst64_tprel_lo12_nc", 0, 32, 0 }, - { "fixup_a64_tlsdesc_adr_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_a64_tlsdesc_ld64_lo12_nc", 0, 32, 0 }, - { "fixup_a64_tlsdesc_add_lo12_nc", 0, 32, 0 }, - { "fixup_a64_tlsdesc_call", 0, 0, 0 } +// Name Offset (bits) Size (bits) Flags +{ "fixup_a64_ld_prel", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_a64_adr_prel", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_a64_adr_prel_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_a64_add_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst8_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst16_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst32_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst64_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst128_lo12", 0, 32, 0 }, +{ "fixup_a64_tstbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_a64_condbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_a64_uncondbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_a64_call", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_a64_movw_uabs_g0", 0, 32, 0 }, +{ "fixup_a64_movw_uabs_g0_nc", 0, 32, 0 }, +{ "fixup_a64_movw_uabs_g1", 0, 32, 0 }, +{ "fixup_a64_movw_uabs_g1_nc", 0, 32, 0 }, +{ "fixup_a64_movw_uabs_g2", 0, 32, 0 }, +{ "fixup_a64_movw_uabs_g2_nc", 0, 32, 0 }, +{ "fixup_a64_movw_uabs_g3", 0, 32, 0 }, +{ "fixup_a64_movw_sabs_g0", 0, 32, 0 }, +{ "fixup_a64_movw_sabs_g1", 0, 32, 0 }, +{ "fixup_a64_movw_sabs_g2", 0, 32, 0 }, +{ "fixup_a64_adr_prel_got_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_a64_ld64_got_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_movw_dtprel_g2", 0, 32, 0 }, +{ "fixup_a64_movw_dtprel_g1", 0, 32, 0 }, +{ "fixup_a64_movw_dtprel_g1_nc", 0, 32, 0 }, +{ "fixup_a64_movw_dtprel_g0", 0, 32, 0 }, +{ "fixup_a64_movw_dtprel_g0_nc", 0, 32, 0 }, +{ "fixup_a64_add_dtprel_hi12", 0, 32, 0 }, +{ "fixup_a64_add_dtprel_lo12", 0, 32, 0 }, +{ "fixup_a64_add_dtprel_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_ldst8_dtprel_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst8_dtprel_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_ldst16_dtprel_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst16_dtprel_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_ldst32_dtprel_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst32_dtprel_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_ldst64_dtprel_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst64_dtprel_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_movw_gottprel_g1", 0, 32, 0 }, +{ "fixup_a64_movw_gottprel_g0_nc", 0, 32, 0 }, +{ "fixup_a64_adr_gottprel_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_a64_ld64_gottprel_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_ld_gottprel_prel19", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_a64_movw_tprel_g2", 0, 32, 0 }, +{ "fixup_a64_movw_tprel_g1", 0, 32, 0 }, +{ "fixup_a64_movw_tprel_g1_nc", 0, 32, 0 }, +{ "fixup_a64_movw_tprel_g0", 0, 32, 0 }, +{ "fixup_a64_movw_tprel_g0_nc", 0, 32, 0 }, +{ "fixup_a64_add_tprel_hi12", 0, 32, 0 }, +{ "fixup_a64_add_tprel_lo12", 0, 32, 0 }, +{ "fixup_a64_add_tprel_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_ldst8_tprel_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst8_tprel_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_ldst16_tprel_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst16_tprel_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_ldst32_tprel_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst32_tprel_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_ldst64_tprel_lo12", 0, 32, 0 }, +{ "fixup_a64_ldst64_tprel_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_tlsdesc_adr_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_a64_tlsdesc_ld64_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_tlsdesc_add_lo12_nc", 0, 32, 0 }, +{ "fixup_a64_tlsdesc_call", 0, 0, 0 } }; if (Kind < FirstTargetFixupKind) return MCAsmBackend::getFixupKindInfo(Kind); |