summaryrefslogtreecommitdiff
path: root/lib/Target/AArch64/MCTargetDesc
diff options
context:
space:
mode:
authorWeiming Zhao <weimingz@codeaurora.org>2014-06-23 20:44:16 +0000
committerWeiming Zhao <weimingz@codeaurora.org>2014-06-23 20:44:16 +0000
commit3cffac50618df11963f9a727a50d80423efb63f9 (patch)
tree1020b8f86da6098366081295a84958cdc2880c49 /lib/Target/AArch64/MCTargetDesc
parent2da970364f190876f204da5fdcf4eb9bce201255 (diff)
downloadllvm-3cffac50618df11963f9a727a50d80423efb63f9.tar.gz
llvm-3cffac50618df11963f9a727a50d80423efb63f9.tar.bz2
llvm-3cffac50618df11963f9a727a50d80423efb63f9.tar.xz
Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64
This patch is based on the changes from ARM target [1,2] Based on ARM doc [3], if the literal value can be loaded with a valid MOV, it can emit that instruction. This is implemented in this patch. [1] Fix PR18345: ldr= pseudo instruction produces incorrect code when using in inline assembly Author: David Peixotto <dpeixott@codeaurora.org> commit b92cca222898d87bbc764fa22e805adb04ef7f13 (r200777) [2] Implement the ldr-pseudo opcode for ARM assembly Author: David Peixotto <dpeixott@codeaurora.org> commit 0fa193b08627927ccaa0804a34d80480894614b8 (r197708) [3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CJAHAIBC.html Differential Revision: http://reviews.llvm.org/D4163 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211533 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/MCTargetDesc')
-rw-r--r--lib/Target/AArch64/MCTargetDesc/CMakeLists.txt1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/AArch64/MCTargetDesc/CMakeLists.txt b/lib/Target/AArch64/MCTargetDesc/CMakeLists.txt
index 7d5bced17a..6d8be5e63f 100644
--- a/lib/Target/AArch64/MCTargetDesc/CMakeLists.txt
+++ b/lib/Target/AArch64/MCTargetDesc/CMakeLists.txt
@@ -7,6 +7,7 @@ add_llvm_library(LLVMAArch64Desc
AArch64MCExpr.cpp
AArch64MCTargetDesc.cpp
AArch64MachObjectWriter.cpp
+ AArch64TargetStreamer.cpp
)
add_dependencies(LLVMAArch64Desc AArch64CommonTableGen)