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| author | Kevin Qin <Kevin.Qin@arm.com> | 2013-12-24 08:11:47 +0000 |
|---|---|---|
| committer | Kevin Qin <Kevin.Qin@arm.com> | 2013-12-24 08:11:47 +0000 |
| commit | 0e8c1f5ca33f413cdd320fd1dcfebdba34b14f06 (patch) | |
| tree | 515b6f35294c6ee79ae2d945b942f43c59ddd8fd /lib/Target/AArch64 | |
| parent | e97b13228a46d1ae76cb77d8749f9867f817ebeb (diff) | |
| download | llvm-0e8c1f5ca33f413cdd320fd1dcfebdba34b14f06.tar.gz llvm-0e8c1f5ca33f413cdd320fd1dcfebdba34b14f06.tar.bz2 llvm-0e8c1f5ca33f413cdd320fd1dcfebdba34b14f06.tar.xz | |
[AArch64 NEON] Fix a pattern match failure with NEON_VDUP.
This failure caused by improper condition when lowering shuffle_vector
to scalar_to_vector. After this patch NEON_VDUP with v1i64 will not
be generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197966 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
| -rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrNEON.td | 10 |
2 files changed, 8 insertions, 6 deletions
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 1b75d0571a..f72dfe46de 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4070,9 +4070,7 @@ AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, if (ValueCounts.size() == 0) return DAG.getUNDEF(VT); - // Loads are better lowered with insert_vector_elt. - // Keep going if we are hitting this case. - if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode())) + if (isOnlyLowElement) return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value); unsigned EltSize = VT.getVectorElementType().getSizeInBits(); diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index 43c2bf48c7..cd063d3d2f 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -3690,12 +3690,16 @@ def : LD1R_pattern<v2f32, f32, load, LD1R_2S>; def : LD1R_pattern<v4i32, i32, load, LD1R_4S>; def : LD1R_pattern<v4f32, f32, load, LD1R_4S>; -def : LD1R_pattern<v1i64, i64, load, LD1R_1D>; -def : LD1R_pattern<v1f64, f64, load, LD1R_1D>; - def : LD1R_pattern<v2i64, i64, load, LD1R_2D>; def : LD1R_pattern<v2f64, f64, load, LD1R_2D>; +class LD1R_pattern_v1 <ValueType VTy, ValueType DTy, PatFrag LoadOp, + Instruction INST> + : Pat<(VTy (scalar_to_vector (DTy (LoadOp GPR64xsp:$Rn)))), + (VTy (INST GPR64xsp:$Rn))>; + +def : LD1R_pattern_v1<v1i64, i64, load, LD1R_1D>; +def : LD1R_pattern_v1<v1f64, f64, load, LD1R_1D>; multiclass VectorList_Bare_BHSD<string PREFIX, int Count, RegisterClass RegList> { |