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| author | Kevin Qin <Kevin.Qin@arm.com> | 2014-02-21 07:45:48 +0000 |
|---|---|---|
| committer | Kevin Qin <Kevin.Qin@arm.com> | 2014-02-21 07:45:48 +0000 |
| commit | 10ecde5c3442cd24c8f13bd29c20a2c48be1bad8 (patch) | |
| tree | b3e9b87e8ecd928e55ca698a15479d9fbd3802a7 /lib/Target/AArch64 | |
| parent | b3cb707f935560e40e2c1b15922910e6246cccf5 (diff) | |
| download | llvm-10ecde5c3442cd24c8f13bd29c20a2c48be1bad8.tar.gz llvm-10ecde5c3442cd24c8f13bd29c20a2c48be1bad8.tar.bz2 llvm-10ecde5c3442cd24c8f13bd29c20a2c48be1bad8.tar.xz | |
[AArch64] Add register constraints to avoid generating STLXR and STXR with unpredictable behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201841 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrInfo.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td index c961fb2c5d..2a3cad0421 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.td +++ b/lib/Target/AArch64/AArch64InstrInfo.td @@ -2596,6 +2596,7 @@ class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, pat, itin> { let mayStore = 1; let PostEncoderMethod = "fixLoadStoreExclusive<1,0>"; + let Constraints = "@earlyclobber $Rs"; } multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> { |