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| author | Alp Toker <alp@nuanti.com> | 2014-05-31 21:26:28 +0000 |
|---|---|---|
| committer | Alp Toker <alp@nuanti.com> | 2014-05-31 21:26:28 +0000 |
| commit | 4a0555250d85f2da6f26881ae9c15bcdb49b1d98 (patch) | |
| tree | 6aec4afeae579e478c872d6d0e6ee0deb12acf43 /lib/Target/AArch64 | |
| parent | ef10f995028c05c2df615eaca4b0bf6017e1ad66 (diff) | |
| download | llvm-4a0555250d85f2da6f26881ae9c15bcdb49b1d98.tar.gz llvm-4a0555250d85f2da6f26881ae9c15bcdb49b1d98.tar.bz2 llvm-4a0555250d85f2da6f26881ae9c15bcdb49b1d98.tar.xz | |
Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209982 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
| -rw-r--r-- | lib/Target/AArch64/AArch64SchedA53.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/AArch64/AArch64SchedA53.td b/lib/Target/AArch64/AArch64SchedA53.td index 0c3949ecfc..d709bee7b9 100644 --- a/lib/Target/AArch64/AArch64SchedA53.td +++ b/lib/Target/AArch64/AArch64SchedA53.td @@ -148,9 +148,9 @@ def : ReadAdvance<ReadVLD, 0>; // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable // operands are needed one cycle later if and only if they are to be -// shifted. Otherwise, they too are needed two cycle later. This same +// shifted. Otherwise, they too are needed two cycles later. This same // ReadAdvance applies to Extended registers as well, even though there is -// a seperate SchedPredicate for them. +// a separate SchedPredicate for them. def : ReadAdvance<ReadI, 2, [WriteImm,WriteI, WriteISReg, WriteIEReg,WriteIS, WriteID32,WriteID64, |