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| author | Hao Liu <Hao.Liu@arm.com> | 2014-01-17 05:44:46 +0000 |
|---|---|---|
| committer | Hao Liu <Hao.Liu@arm.com> | 2014-01-17 05:44:46 +0000 |
| commit | 555f57f67b4a6dd1738f42cdf8c8499461edec7c (patch) | |
| tree | 6b77da2f6099843b9679f84cfcf696c0d02054e0 /lib/Target/AArch64 | |
| parent | 008425f5da940a5f696f90db72dae402188e165b (diff) | |
| download | llvm-555f57f67b4a6dd1738f42cdf8c8499461edec7c.tar.gz llvm-555f57f67b4a6dd1738f42cdf8c8499461edec7c.tar.bz2 llvm-555f57f67b4a6dd1738f42cdf8c8499461edec7c.tar.xz | |
[AArch64]Fix the problem can't select concat_vectors of two v1i32 types.
Also fix the problem can't select scalar_to_vector from f32 to v2f32/v4f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199461 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
| -rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrNEON.td | 18 |
2 files changed, 10 insertions, 12 deletions
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 581c8935c1..00a4ac6a8f 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -324,13 +324,11 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM) setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1f64, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); + setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i32, Legal); setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Legal); setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Legal); setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Legal); setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Legal); - setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Legal); - setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Legal); - setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Legal); setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Legal); setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Legal); diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index 81371be066..251fee2af2 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -6888,15 +6888,10 @@ def : Pat<(v4i32 (scalar_to_vector GPR32:$Rn)), def : Pat<(v2i64 (scalar_to_vector GPR64:$Rn)), (INSdx (v2i64 (IMPLICIT_DEF)), $Rn, (i64 0))>; -def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)), - (v2i32 (EXTRACT_SUBREG (v16i8 - (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))), - sub_64))>; - -def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)), - (v2i32 (EXTRACT_SUBREG (v16i8 - (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))), - sub_64))>; +def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))), + (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)>; +def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))), + (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)>; def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))), (v1f64 FPR64:$Rn)>; @@ -7063,6 +7058,11 @@ defm : Concat_Vector_Pattern<v2i64, v1i64>; defm : Concat_Vector_Pattern<v4f32, v2f32>; defm : Concat_Vector_Pattern<v2f64, v1f64>; +def : Pat<(v2i32 (concat_vectors (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rn))), + (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>; +def : Pat<(v2i32 (concat_vectors undef, (v1i32 FPR32:$Rn))), + (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>; + //patterns for EXTRACT_SUBVECTOR def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))), (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>; |