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| author | Hao Liu <Hao.Liu@arm.com> | 2013-12-12 07:36:26 +0000 |
|---|---|---|
| committer | Hao Liu <Hao.Liu@arm.com> | 2013-12-12 07:36:26 +0000 |
| commit | 60a21f2238282dcc6f6f06617e6adf09b1c7586c (patch) | |
| tree | 1a412452e57c24fa041eee7477bdca0a6052440c /lib/Target/AArch64 | |
| parent | 7f8ef1ecc4004068f9178e932bdb0fa1c2b527d2 (diff) | |
| download | llvm-60a21f2238282dcc6f6f06617e6adf09b1c7586c.tar.gz llvm-60a21f2238282dcc6f6f06617e6adf09b1c7586c.tar.bz2 llvm-60a21f2238282dcc6f6f06617e6adf09b1c7586c.tar.xz | |
[AArch64]Fix the problem that AArch64 backend fails to select scalar_to_vector of vector types having more than one element.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197135 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrNEON.td | 40 |
1 files changed, 37 insertions, 3 deletions
diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index 6a2c79de6b..9dd3e41c31 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -6707,14 +6707,48 @@ def : Pat<(v1i32 (scalar_to_vector GPR32:$src)), def : Pat<(v1i64 (scalar_to_vector GPR64:$src)), (FMOVdx $src)>; +def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)), + (v8i8 (EXTRACT_SUBREG (v16i8 + (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))), + sub_64))>; + +def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)), + (v4i16 (EXTRACT_SUBREG (v8i16 + (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))), + sub_64))>; + +def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)), + (v2i32 (EXTRACT_SUBREG (v16i8 + (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))), + sub_64))>; + +def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)), + (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))>; + +def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)), + (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))>; + +def : Pat<(v4i32 (scalar_to_vector GPR32:$Rn)), + (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))>; + +def : Pat<(v2i64 (scalar_to_vector GPR64:$Rn)), + (INSdx (v2i64 (IMPLICIT_DEF)), $Rn, (i64 0))>; + +def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)), + (v2i32 (EXTRACT_SUBREG (v16i8 + (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))), + sub_64))>; + +def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)), + (v2i32 (EXTRACT_SUBREG (v16i8 + (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))), + sub_64))>; + def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))), (v1f32 FPR32:$Rn)>; def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))), (v1f64 FPR64:$Rn)>; -def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))), - (FMOVdd $src)>; - def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))), (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), (f64 FPR64:$src), sub_64)>; |