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| author | Chad Rosier <mcrosier@codeaurora.org> | 2013-12-11 21:03:43 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2013-12-11 21:03:43 +0000 |
| commit | 73f468218fc56a0acf9cb9c38eb74b138e955ff5 (patch) | |
| tree | 9909a700335d59b93b079dfb6ce0f9de7ae33099 /lib/Target/AArch64 | |
| parent | c3e5d72ba83f607d7e1409027f7593c689fc70d0 (diff) | |
| download | llvm-73f468218fc56a0acf9cb9c38eb74b138e955ff5.tar.gz llvm-73f468218fc56a0acf9cb9c38eb74b138e955ff5.tar.bz2 llvm-73f468218fc56a0acf9cb9c38eb74b138e955ff5.tar.xz | |
[AArch64] Refactor the NEON scalar floating-point reciprocal step and
floating-point reciprocal square root step LLVM AArch64 intrinsics to
use f32/f64 types, rather than their vector equivalents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197067 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrNEON.td | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index 9e02dc4fff..f9d404252b 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -4187,11 +4187,14 @@ multiclass Neon_Scalar3Same_fabd_SD_size_patterns<SDPatternOperator opnode, } multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode, + SDPatternOperator opnodeV, Instruction INSTS, Instruction INSTD> { - def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))), + def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))), (INSTS FPR32:$Rn, FPR32:$Rm)>; - def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), + def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))), + (INSTD FPR64:$Rn, FPR64:$Rm)>; + def : Pat<(v1f64 (opnodeV (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), (INSTD FPR64:$Rn, FPR64:$Rm)>; } @@ -4874,18 +4877,15 @@ defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>; // Scalar Floating-point Reciprocal Step defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>; +defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrecps, + int_arm_neon_vrecps, FRECPSsss, + FRECPSddd>; // Scalar Floating-point Reciprocal Square Root Step defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>; - -// Patterns to match llvm.arm.* intrinsic for -// Scalar Floating-point Reciprocal Step and -// Scalar Floating-point Reciprocal Square Root Step -defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrecps, FRECPSsss, - FRECPSddd>; -defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss, - FRSQRTSddd>; - +defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrsqrts, + int_arm_neon_vrsqrts, FRSQRTSsss, + FRSQRTSddd>; def : Pat<(v1f64 (fsqrt (v1f64 FPR64:$Rn))), (FSQRTdd FPR64:$Rn)>; // Patterns to match llvm.aarch64.* intrinsic for |