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| author | Jiangning Liu <jiangning.liu@arm.com> | 2014-01-26 04:55:53 +0000 |
|---|---|---|
| committer | Jiangning Liu <jiangning.liu@arm.com> | 2014-01-26 04:55:53 +0000 |
| commit | da77e83632de1c5519f2b55986b3431583f0d866 (patch) | |
| tree | 1aa91d0b44dcb4d2259dd322107329af67066c9a /lib/Target/AArch64 | |
| parent | e1631e8729efb02146d6d3866f542f57ad50c84c (diff) | |
| download | llvm-da77e83632de1c5519f2b55986b3431583f0d866.tar.gz llvm-da77e83632de1c5519f2b55986b3431583f0d866.tar.bz2 llvm-da77e83632de1c5519f2b55986b3431583f0d866.tar.xz | |
Improve pattern match from v1i8 to v1i32 for AArch64 Neon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200119 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrNEON.td | 34 |
1 files changed, 22 insertions, 12 deletions
diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index 1180485b72..3056343abb 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -6233,23 +6233,21 @@ multiclass NeonI_ext<string prefix, SDNode ExtOp> { (v8i16 (!cast<Instruction>(prefix # "_8B") (v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)), sub_16)>; - - // v1i8 -> v1i32 - def : Pat<(v1i32 (ExtOp (v1i8 FPR8:$Rn))), - (EXTRACT_SUBREG - (v4i32 (!cast<Instruction>(prefix # "_4H") - (v4i16 (SUBREG_TO_REG (i64 0), - (v1i16 (EXTRACT_SUBREG - (v8i16 (!cast<Instruction>(prefix # "_8B") - (v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)), - sub_16)), - sub_16)), 0)), - sub_32)>; } defm NeonI_zext : NeonI_ext<"USHLLvvi", zext>; defm NeonI_sext : NeonI_ext<"SSHLLvvi", sext>; +// zext v1i8 -> v1i32 +def : Pat<(v1i32 (zext (v1i8 FPR8:$Rn))), + (v1i32 (EXTRACT_SUBREG + (v1i64 (SUBREG_TO_REG (i64 0), + (v1i8 (DUPbv_B + (v16i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), + 0)), + sub_8)), + sub_32))>; + // zext v1i8 -> v1i64 def : Pat<(v1i64 (zext (v1i8 FPR8:$Rn))), (v1i64 (SUBREG_TO_REG (i64 0), @@ -6266,6 +6264,18 @@ def : Pat<(v1i64 (zext (v1i16 FPR16:$Rn))), 0)), sub_16))>; +// sext v1i8 -> v1i32 +def : Pat<(v1i32 (sext (v1i8 FPR8:$Rn))), + (EXTRACT_SUBREG + (v4i32 (SSHLLvvi_4H + (v4i16 (SUBREG_TO_REG (i64 0), + (v1i16 (EXTRACT_SUBREG + (v8i16 (SSHLLvvi_8B + (v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)), + sub_16)), + sub_16)), 0)), + sub_32)>; + // sext v1i8 -> v1i64 def : Pat<(v1i64 (sext (v1i8 FPR8:$Rn))), (EXTRACT_SUBREG |