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authorBernard Ogden <bogden@arm.com>2013-10-14 13:17:07 +0000
committerBernard Ogden <bogden@arm.com>2013-10-14 13:17:07 +0000
commit0d1e2aebe641fc26bba5d895bbcadcac6f23aaec (patch)
treee9888ab14670249e03263cbbdf587a7cd42d1ce3 /lib/Target/ARM/ARM.td
parent7220572e74844aa37b1b492ef67a8c1b403a254f (diff)
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Add Cortex-A57 support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192591 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARM.td')
-rw-r--r--lib/Target/ARM/ARM.td9
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index 9de29c1cb1..5fab93040c 100644
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -203,6 +203,12 @@ def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
FeatureTrustZone, FeatureT2XtPk,
FeatureCrypto]>;
+def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
+ "Cortex-A57 ARM processors",
+ [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
+ FeatureTrustZone, FeatureT2XtPk,
+ FeatureCrypto]>;
+
def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
"Cortex-R5 ARM processors",
[FeatureSlowFPBrcc,
@@ -326,6 +332,9 @@ def : ProcessorModel<"swift", SwiftModel,
def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
FeatureDB, FeatureFPARMv8,
FeatureNEON, FeatureDSPThumb2]>;
+def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
+ FeatureDB, FeatureFPARMv8,
+ FeatureNEON, FeatureDSPThumb2]>;
//===----------------------------------------------------------------------===//
// Register File Description