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authorEli Bendersky <eliben@google.com>2013-01-30 16:30:19 +0000
committerEli Bendersky <eliben@google.com>2013-01-30 16:30:19 +0000
commit0f156af8312a0f3ce88e5c006bf2a52691039ceb (patch)
treed234b449bdb269b7fa099f4f636d2ed07f359925 /lib/Target/ARM/ARM.td
parent620d5bd8e43331a9b5ba2437c1de0d3f4a43a34d (diff)
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Add a special ARM trap encoding for NaCl.
More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARM.td')
-rw-r--r--lib/Target/ARM/ARM.td5
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index a76715a092..46915eecf6 100644
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -110,6 +110,11 @@ def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
"Is microcontroller profile ('M' series)">;
+// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
+// See ARMInstrInfo.td for details.
+def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
+ "NaCl trap">;
+
// ARM ISAs.
def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
"Support ARM v4T instructions">;