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| author | Evan Cheng <evan.cheng@apple.com> | 2010-08-11 06:22:01 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-08-11 06:22:01 +0000 |
| commit | 11db068721d44fd5f9b0c2a3a4c90f813d2eae9c (patch) | |
| tree | 7649fa37f8869eb5f872a3d73eb58587295b6cf1 /lib/Target/ARM/ARM.td | |
| parent | 3483acabf012b847b13b969ebd9ce5c4d16d9eb7 (diff) | |
| download | llvm-11db068721d44fd5f9b0c2a3a4c90f813d2eae9c.tar.gz llvm-11db068721d44fd5f9b0c2a3a4c90f813d2eae9c.tar.bz2 llvm-11db068721d44fd5f9b0c2a3a4c90f813d2eae9c.tar.xz | |
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARM.td')
| -rw-r--r-- | lib/Target/ARM/ARM.td | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index e76a47dff9..d1e84cdd4a 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -48,6 +48,8 @@ def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", "Enable divide instructions">; def FeatureT2ExtractPack: SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", "Enable Thumb2 extract and pack instructions">; +def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", + "Has data barrier (dmb / dsb) instructions">; def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", "FP compare + branch is slow">; @@ -134,11 +136,15 @@ def : Processor<"arm1156t2f-s", ARMV6Itineraries, // V7 Processors. def : Processor<"cortex-a8", CortexA8Itineraries, [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx, - FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2ExtractPack]>; + FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2ExtractPack, + FeatureDB]>; def : Processor<"cortex-a9", CortexA9Itineraries, - [ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2ExtractPack]>; -def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2, FeatureHWDiv]>; -def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureThumb2, FeatureHWDiv]>; + [ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2ExtractPack, + FeatureDB]>; +def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2, FeatureHWDiv, + FeatureDB]>; +def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureThumb2, FeatureHWDiv, + FeatureDB]>; //===----------------------------------------------------------------------===// // Register File Description |