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author | Bob Wilson <bob.wilson@apple.com> | 2011-04-19 18:11:49 +0000 |
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committer | Bob Wilson <bob.wilson@apple.com> | 2011-04-19 18:11:49 +0000 |
commit | 5dde893c2bac9e1569c38429f756c1d723e8edf2 (patch) | |
tree | c50cc65135cde589cb7ccb40f829b18e1c9b3454 /lib/Target/ARM/ARM.td | |
parent | f6a4d3c2f3e1029af252a0f6999edfa3c2f326ee (diff) | |
download | llvm-5dde893c2bac9e1569c38429f756c1d723e8edf2.tar.gz llvm-5dde893c2bac9e1569c38429f756c1d723e8edf2.tar.bz2 llvm-5dde893c2bac9e1569c38429f756c1d723e8edf2.tar.xz |
Avoid some 's' 16-bit instruction which partially update CPSR
(and add false dependency) when it isn't dependent on last CPSR defining
instruction. rdar://8928208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129773 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARM.td')
-rw-r--r-- | lib/Target/ARM/ARM.td | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index e690e18672..133af31a38 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -67,6 +67,14 @@ def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", "Prefer 32-bit Thumb instrs">; +/// Some instructions update CPSR partially, which can add false dependency for +/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is +/// mapped to a separate physical register. Avoid partial CPSR update for these +/// processors. +def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", + "AvoidCPSRPartialUpdate", "true", + "Avoid CPSR partial update for OOO execution">; + // Multiprocessing extension. def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", "Supports Multiprocessing extension">; @@ -111,7 +119,8 @@ def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", "Cortex-A9 ARM processors", [FeatureHasSlowFPVMLx, FeatureVMLxForwarding, - FeatureT2XtPk, FeatureFP16]>; + FeatureT2XtPk, FeatureFP16, + FeatureAvoidPartialCPSR]>; class ProcNoItin<string Name, list<SubtargetFeature> Features> : Processor<Name, GenericItineraries, Features>; |