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| author | Bradley Smith <bradley.smith@arm.com> | 2013-11-01 13:27:35 +0000 |
|---|---|---|
| committer | Bradley Smith <bradley.smith@arm.com> | 2013-11-01 13:27:35 +0000 |
| commit | 6186de5c54b580414b2d162e0f335b62b3d9812c (patch) | |
| tree | b3344d5f6878a35572e91d1bd11679795623afed /lib/Target/ARM/ARM.td | |
| parent | 479a2de32a994b1902869b88e56253936d943531 (diff) | |
| download | llvm-6186de5c54b580414b2d162e0f335b62b3d9812c.tar.gz llvm-6186de5c54b580414b2d162e0f335b62b3d9812c.tar.bz2 llvm-6186de5c54b580414b2d162e0f335b62b3d9812c.tar.xz | |
[ARM] Add Virtualization subtarget feature and more build attributes in this area
Add a Virtualization ARM subtarget feature along with adding proper build
attribute emission for Tag_Virtualization_use (encodes Virtualization and
TrustZone) and Tag_MPextension_use.
Also rework test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll testcase to
something that is more maintainable. This changes the focus of this
testcase away from testing CPU defaults (which is tested elsewhere), onto
specifically testing that attributes are encoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193859 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARM.td')
| -rw-r--r-- | lib/Target/ARM/ARM.td | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 3bf81828bf..36e5680ca4 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -119,6 +119,12 @@ def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true", def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", "Supports Multiprocessing extension">; +// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). +def FeatureVirtualization : SubtargetFeature<"virtualization", + "HasVirtualization", "true", + "Supports Virtualization extension", + [FeatureHWDiv, FeatureHWDivARM]>; + // M-series ISA def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", "Is microcontroller profile ('M' series)">; @@ -159,7 +165,8 @@ def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", [HasV6T2Ops, FeaturePerfMon]>; def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", "Support ARM v8 instructions", - [HasV7Ops]>; + [HasV7Ops, FeatureVirtualization, + FeatureMP]>; //===----------------------------------------------------------------------===// // ARM Processors supported. @@ -198,17 +205,17 @@ def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", [FeatureT2XtPk, FeatureVFP4, FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureAvoidPartialCPSR, - FeatureTrustZone]>; + FeatureTrustZone, FeatureVirtualization]>; def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", "Cortex-A53 ARM processors", - [FeatureMP, FeatureHWDiv, FeatureHWDivARM, + [FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, FeatureT2XtPk, FeatureCrypto, FeatureCRC]>; def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", "Cortex-A57 ARM processors", - [FeatureMP, FeatureHWDiv, FeatureHWDivARM, + [FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, FeatureT2XtPk, FeatureCrypto, FeatureCRC]>; |